Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005LFENCELoad FenceActs as a barrier to force strong memory ordering (serialization) between loadinstructions preceding the LFENCE and load instructions that follow the LFENCE. Aweakly-ordered memory system allows hardware to reorder reads and writes betweenthe processor and memory. The LFENCE instruction guarantees that the systemcompletes all previous loads before executing subsequent loads.The LFENCE instruction is weakly-ordered with respect to store instructions, dataand instruction prefetches, and the SFENCE instruction. Speculative loads initiatedby the processor, or specified explicitly using cache-prefetch instructions, can bereordered around an LFENCE.In addition to load instructions, the LFENCE instruction is strongly ordered withrespect to other LFENCE instructions, MFENCE instructions, and serializinginstructions.Support for the LFENCE instruction is indicated when the SSE2 bit (bit 26) is set to 1in EDX after executing CPUID standard function 1.Mnemonic Opcode DescriptionLFENCE 0F AE E8 Force strong ordering of (serialize) load operations.Related InstructionsMFENCE, SFENCErFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The LFENCE instruction is not supported as indicated by EDX bit 26of CPUID standard function 1.186 LFENCE
24594 Rev. 3.10 February 2005 AMD64 TechnologyLODSLODSBLODSWLODSDLODSQLoad StringCopies the byte, word, doubleword, or quadword in the memory location pointed to bythe DS:rSI registers to the AL, AX, EAX, or RAX register, depending on the size of theoperand, and then increments or decrements the rSI register according to the state ofthe DF flag in the rFLAGS register.If the DF flag is 0, the instruction increments rSI; otherwise, it decrements rSI. Itincrements or decrements rSI by 1, 2, 4, or 8, depending on the number of bytes beingloaded.The forms of the LODS instruction with an explicit operand address the operand atseg:[rSI]. The value of seg defaults to the DS segment, but may be overridden by asegment prefix. The explicit operand serves only to specify the type (size) of the valuebeing copied and the specific registers used.The no-operands forms of the instruction always use the DS:[rSI] registers to point tothe value to be copied (they do not allow a segment prefix). The mnemonic determinesthe size of the operand and the specific registers used.The LODSx instructions support the REP prefixes. For details about the REP prefixes,see “Repeat Prefixes” on page 10. More often, software uses the LODSx instructioninside a loop controlled by a LOOPcc instruction as a more efficient replacement forinstructions like:mov eax, dword ptr ds:[esi]add esi, 4The LODSQ instruction can only be used in 64-bit mode.Mnemonic Opcode DescriptionLODS mem8 AC Load byte at DS:rSI into AL and then increment or decrement rSI.LODS mem16LODS mem32ADADLoad word at DS:rSI into AX and then increment or decrementrSI.Load doubleword at DS:rSI into EAX and then increment ordecrement rSI.LODSx 187
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AMD64 Technology 24594 Rev. 3.10 February 2005LFENCELoad FenceActs as a barrier to force strong memory ordering (serialization) between loadinstructions preceding the LFENCE <strong>and</strong> load instructions that follow the LFENCE. Aweakly-ordered memory system allows hardware to reorder reads <strong>and</strong> writes betweenthe processor <strong>and</strong> memory. The LFENCE instruction guarantees that the systemcompletes all previous loads before executing subsequent loads.The LFENCE instruction is weakly-ordered with respect to store instructions, data<strong>and</strong> instruction prefetches, <strong>and</strong> the SFENCE instruction. Speculative loads initiatedby the processor, or specified explicitly using cache-prefetch instructions, can bereordered around an LFENCE.In addition to load instructions, the LFENCE instruction is strongly ordered withrespect to other LFENCE instructions, MFENCE instructions, <strong>and</strong> serializinginstructions.Support for the LFENCE instruction is indicated when the SSE2 bit (bit 26) is set to 1in EDX after executing CPUID st<strong>and</strong>ard function 1.Mnemonic Opcode DescriptionLFENCE 0F AE E8 Force strong ordering of (serialize) load operations.Related <strong>Instructions</strong>MFENCE, SFENCErFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The LFENCE instruction is not supported as indicated by EDX bit 26of CPUID st<strong>and</strong>ard function 1.186 LFENCE
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