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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005LAHFLoad Status Flags into AH RegisterLoads the lower 8 bits of the rFLAGS register, including sign flag (SF), zero flag (ZF),auxiliary carry flag (AF), parity flag (PF), <strong>and</strong> carry flag (CF), into the AH register.The instruction sets the reserved bits 1, 3, <strong>and</strong> 5 of the rFLAGS register to 1, 0, <strong>and</strong> 0,respectively, in the AH register.The LAHF instruction can only be executed in 64-bit mode if supported by theprocessor implementation. Check the status of ECX bit 0 returned by CPUIDextended function 8000_0001h to verify that the processor supports LAHF in 64-bitmode.Mnemonic Opcode DescriptionLAHF 9F Load the SF, ZF, AF, PF, <strong>and</strong> CF flags into the AH register.Related <strong>Instructions</strong>SAHFrFLAGS AffectedExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X This instruction is not supported in 64-bit mode, as indicated by ECXbit 0 returned by CPUID st<strong>and</strong>ard function 8000_0001h.178 LAHF

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