Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionJGE rel8offJGE rel16offJGE rel32offJLE rel8offJLE rel16offJLE rel32offJNG rel8offJNG rel16offJNG rel32offJNLE rel8offJNLE rel16offJNLE rel32offJG rel8offJG rel16offJG rel32offRelated Instructions7D cb0F 8D cw0F 8D cd7E cb0F 8E cw0F 8E cd7E cb0F 8E cw0F 8E cd7F cb0F 8F cw0F 8F cd7F cb0F 8F cw0F 8F cdJump if greater or equal (SF = OF).Jump if less or equal (ZF = 1 or SF OF).Jump if not greater (ZF = 1 or SF OF).Jump if not less or equal (ZF = 0 and SF = OF).Jump if greater (ZF = 0 and SF = OF).JMP (Near), JMP (Far), JrCXZrFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X X The target offset exceeded the code segment limit or was non-canonical.168 Jcc
24594 Rev. 3.10 February 2005 AMD64 TechnologyJCXZJECXZJRCXZJump if rCX ZeroChecks the contents of the count register (rCX) and, if 0, jumps to the targetinstruction located at the specified 8-bit relative offset. Otherwise, executioncontinues with the instruction following the JrCXZ instruction.The size of the count register (CX, ECX, or RCX) depends on the address-sizeattribute of the JrCXZ instruction. Therefore, JRCXZ can only be executed in 64-bitmode and JCXZ cannot be executed in 64-bit mode.If the jump is taken, the signed displacement is added to the rIP (of the followinginstruction) and the result is truncated to 16, 32, or 64 bits, depending on operandsize.In 64-bit mode, the operand size defaults to 64 bits. The processor sign-extends the 8-bit displacement value to 64 bits before adding it to the RIP.For details about control-flow instructions, see “Control Transfers” in Volume 1, and“Control-Transfer Privilege Checks” in Volume 2.Mnemonic Opcode DescriptionJCXZ rel8off E3 cb Jump short if the 16-bit count register (CX) is zero.JECXZ rel8off E3 cb Jump short if the 32-bit count register (ECX) is zero.JRCXZ rel8off E3 cb Jump short if the 64-bit count register (RCX) is zero.Related InstructionsJcc, JMP (Near), JMP (Far)rFLAGS AffectedNoneJrCXZ 169
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24594 Rev. 3.10 February 2005 AMD64 TechnologyJCXZJECXZJRCXZJump if rCX ZeroChecks the contents of the count register (rCX) <strong>and</strong>, if 0, jumps to the targetinstruction located at the specified 8-bit relative offset. Otherwise, executioncontinues with the instruction following the JrCXZ instruction.The size of the count register (CX, ECX, or RCX) depends on the address-sizeattribute of the JrCXZ instruction. Therefore, JRCXZ can only be executed in 64-bitmode <strong>and</strong> JCXZ cannot be executed in 64-bit mode.If the jump is taken, the signed displacement is added to the rIP (of the followinginstruction) <strong>and</strong> the result is truncated to 16, 32, or 64 bits, depending on oper<strong>and</strong>size.In 64-bit mode, the oper<strong>and</strong> size defaults to 64 bits. The processor sign-extends the 8-bit displacement value to 64 bits before adding it to the RIP.For details about control-flow instructions, see “Control Transfers” in <strong>Volume</strong> 1, <strong>and</strong>“Control-Transfer Privilege Checks” in <strong>Volume</strong> 2.Mnemonic Opcode DescriptionJCXZ rel8off E3 cb Jump short if the 16-bit count register (CX) is zero.JECXZ rel8off E3 cb Jump short if the 32-bit count register (ECX) is zero.JRCXZ rel8off E3 cb Jump short if the 64-bit count register (RCX) is zero.Related <strong>Instructions</strong>Jcc, JMP (Near), JMP (Far)rFLAGS AffectedNoneJrCXZ 169
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