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AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsExceptionInvalid TSS, #TS(selector)RealVirtual8086 Protected Cause of ExceptionXXAs part of a stack switch, the target stack segment selector or rSP inthe TSS was beyond the TSS limit.XXXXXXXXXXAs part of a stack switch, the target stack segment selector in the TSSwas a null selector.As part of a stack switch, the target stack segment selector’s TI bit wasset, but the LDT selector was a null selector.As part of a stack switch, the target stack segment selector in the TSSwas beyond the limit of the GDT or LDT descriptor table.As part of a stack switch, the target stack segment selector in the TSScontained a RPL that was not equal to its DPL.As part of a stack switch, the target stack segment selector in the TSScontained a DPL that was not equal to the CPL of the code segmentselector.Segment not present,#NP (selector)XXAs part of a stack switch, the target stack segment selector in the TSSwas not a writable segment.X X The accessed code segment, interrupt gate, trap gate, task gate, orTSS was not present.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical,and no stack switch occurred.Stack, #SS(selector)XXAfter a stack switch, a memory address exceeded the stack segmentlimit or was non-canonical.General protection,#GPXXXXXAs part of a stack switch, the SS register was loaded with a non-nullsegment selector and the segment was marked not present.A memory address exceeded a data segment limit or was non-canonical.XXXThe target offset exceeded the code segment limit or was non-canonical.XThe IOPL was less than 3 and CR4.VME was 0.XIOPL was less than 3, CR4.VME was 1, and the corresponding bit inthe VME interrupt redirection bitmap was 1.162 INT
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionGeneral protection,#GP(selector)RealXVirtual8086 Protected Cause of ExceptionXXXXThe interrupt vector was beyond the limit of IDT.The descriptor in the IDT was not an interrupt, trap, or task gate inlegacy mode or not a 64-bit interrupt or trap gate in long mode.XXXXXXXXXThe DPL of the interrupt, trap, or task gate descriptor was less thanthe CPL.The segment selector specified by the interrupt or trap gate had its TIbit set, but the LDT selector was a null selector.The segment descriptor specified by the interrupt or trap gateexceeded the descriptor table limit or was a null selector.The segment descriptor specified by the interrupt or trap gate wasnot a code segment in legacy mode, or not a 64-bit code segment inlong mode.The DPL of the segment specified by the interrupt or trap gate wasgreater than the CPL.XThe DPL of the segment specified by the interrupt or trap gatepointed was not 0 or it was a conforming segment.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.INT 163
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