Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005INTInterrupt to VectorTransfers execution to the interrupt handler specified by an 8-bit unsigned immediatevalue. This value is an interrupt vector number (00h to FFh), which the processor usesas an index into the interrupt-descriptor table (IDT).For detailed descriptions of the steps performed by INTn instructions, see thefollowing:• Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” inVolume 2.• Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.See also the descriptions of the INT3 instruction on page 304 and the INTOinstruction on page 164.Mnemonic Opcode DescriptionINT imm8 CD ib Call interrupt service routine specified by interrupt vector imm8.Action// See “Pseudocode Definitions” on page 49.INT_N_START:IF (REAL_MODE)INT_N_REALELSIF (PROTECTED_MODE)INT_N_PROTECTEDELSE // (VIRTUAL_MODE)INT_N_VIRTUALINT_N_REAL:temp_int_n_vector = byte-sized interrupt vector specified in the instruction,zero-extended to 64 bitstemp_RIP = READ_MEM.w [idt:temp_int_n_vector*4]// read target CS:RIP from the real-mode idttemp_CS = READ_MEM.w [idt:temp_int_n_vector*4+2]PUSH.w old_RFLAGSPUSH.w old_CSPUSH.w next_RIP156 INT
24594 Rev. 3.10 February 2005 AMD64 TechnologyIF (temp_RIP>CS.limit)EXCEPTION [#GP]CS.sel = temp_CSCS.base = temp_CS SHL 4RFLAGS.AC,TF,IF,RF clearedRIP = temp_RIPEXITINT_N_PROTECTED:temp_int_n_vector = byte-sized interrupt vector specified in the instruction,zero-extended to 64 bitstemp_idt_desc = READ_IDT (temp_int_n_vector)IF (temp_idt_desc.attr.type = ’taskgate’)TASK_SWITCH // using tss selector in the task gate as the target tssIF (LONG_MODE) // The size of the gate controls the size of the// stack pushes.V=8-byte // Long mode only uses 64-bit gates.ELSIF ((temp_idt_desc.attr.type = ’intgate32’)|| (temp_idt_desc.attr.type = ’trapgate32’))V=4-byte // Legacy mode, using a 32-bit gateELSE // gate is intgate16 or trapgate16V=2-byte // Legacy mode, using a 16-bit gatetemp_RIP = temp_idt_desc.offsetIF (LONG_MODE){// In long mode, we need to read the 2nd half of a// 16-byte interrupt-gate from the IDT, to get the// upper 32 bits of the target RIPtemp_upper = READ_MEM.q [idt:temp_int_n_vector*16+8]}temp_RIP = tempRIP + (temp_upper SHL 32) // concatenate both halves of RIPCS = READ_DESCRIPTOR (temp_idt_desc.segment, intcs_chk)IF (CS.attr.conforming=1)temp_CPL = CPLELSEtemp_CPL = CS.attr.dplIF (CPL=temp_CPL){IF (LONG_MODE)// no privilege-level changeINT 157
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24594 Rev. 3.10 February 2005 AMD64 TechnologyIF (temp_RIP>CS.limit)EXCEPTION [#GP]CS.sel = temp_CSCS.base = temp_CS SHL 4RFLAGS.AC,TF,IF,RF clearedRIP = temp_RIPEXITINT_N_PROTECTED:temp_int_n_vector = byte-sized interrupt vector specified in the instruction,zero-extended to 64 bitstemp_idt_desc = READ_IDT (temp_int_n_vector)IF (temp_idt_desc.attr.type = ’taskgate’)TASK_SWITCH // using tss selector in the task gate as the target tssIF (LONG_MODE) // The size of the gate controls the size of the// stack pushes.V=8-byte // Long mode only uses 64-bit gates.ELSIF ((temp_idt_desc.attr.type = ’intgate32’)|| (temp_idt_desc.attr.type = ’trapgate32’))V=4-byte // Legacy mode, using a 32-bit gateELSE // gate is intgate16 or trapgate16V=2-byte // Legacy mode, using a 16-bit gatetemp_RIP = temp_idt_desc.offsetIF (LONG_MODE){// In long mode, we need to read the 2nd half of a// 16-byte interrupt-gate from the IDT, to get the// upper 32 bits of the target RIPtemp_upper = READ_MEM.q [idt:temp_int_n_vector*16+8]}temp_RIP = tempRIP + (temp_upper SHL 32) // concatenate both halves of RIPCS = READ_DESCRIPTOR (temp_idt_desc.segment, intcs_chk)IF (CS.attr.conforming=1)temp_CPL = CPLELSEtemp_CPL = CS.attr.dplIF (CPL=temp_CPL){IF (LONG_MODE)// no privilege-level changeINT 157
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