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AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionXOne or more I/O permission bits were set in the TSS for the accessedport.X The CPL was greater than the IOPL and one or more I/O permissionbits were set in the TSS for the accessed port.Page fault, #PF X X A page fault resulted from the execution of the instruction.150 IN
24594 Rev. 3.10 February 2005 AMD64 TechnologyINC Increment by 1Adds 1 to the specified register or memory location. The CF flag is not affected, evenif the operand is incremented to 0000.The one-byte forms of this instruction (opcodes 40 through 47) are used as REXprefixes in 64-bit mode. See “REX Prefixes” on page 14.The forms of the INC instruction that write to memory support the LOCK prefix. Fordetails about the LOCK prefix, see “Lock Prefix” on page 10.To perform an increment operation that updates the CF flag, use an ADD instructionwith an immediate operand of 1.Mnemonic Opcode DescriptionINC reg/mem8 FE /0INC reg/mem16 FF /0INC reg/mem32 FF /0INC reg/mem64 FF /0Increment the contents of an 8-bit register or memory locationby 1.Increment the contents of a 16-bit register or memory location by1.Increment the contents of a 32-bit register or memory location by1.Increment the contents of a 64-bit register or memory locationby 1.INC reg16INC reg3240 +rw40 +rdIncrement the contents of a 16-bit register by 1.(These opcodes are used as REX prefixes in 64-bit mode. See“REX Prefixes” on page 14.)Increment the contents of a 32-bit register by 1.(These opcodes are used as REX prefixes in 64-bit mode.See“REX Prefixes” on page 14.)Related InstructionsADD, DECINC 151
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