Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM U U U U M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.148 IMUL
24594 Rev. 3.10 February 2005 AMD64 TechnologyINInput from PortTransfers a byte, word, or doubleword from an I/O port (second operand) to the AL,AX or EAX register (first operand). The port address can be an 8-bit immediate value(00h to FFh) or contained in the DX register (0000h to FFFFh).The port is in the processor’s I/O address space. For 8-bit I/O port accesses, the opcodedetermines the port size. For 16-bit and 32-bit accesses, the operand-size attributedetermines the port size. If the operand size is 64-bits, IN reads only 32 bits from theI/O port.If the CPL is higher than IOPL, or the mode is virtual mode, IN checks the I/Opermission bitmap in the TSS before allowing access to the I/O port. (See Volume 2 fordetails on the TSS I/O permission bitmap.)Mnemonic Opcode DescriptionIN AL, imm8IN AX, imm8IN EAX, imm8IN AL, DXIN AX, DXIN EAX, DXRelated InstructionsINSx, OUT, OUTSxrFLAGS AffectedNoneE4 ibE5 ibE5 ibECEDEDInput a byte from the port at the address specified by imm8 andput it into the AL register.Input a word from the port at the address specified by imm8 andput it into the AX register.Input a doubleword from the port at the address specified byimm8 and put it into the EAX register.Input a byte from the port at the address specified by the DXregister and put it into the AL register.Input a word from the port at the address specified by the DXregister and put it into the AX register.Input a doubleword from the port at the address specified by theDX register and put it into the EAX register.IN 149
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AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM U U U U M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.148 IMUL
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