Volume 3: General-Purpose and System Instructions - Stanford ...

AMD64 Technology 24594 Rev. 3.10 February 2005DIVUnsigned DivideDivides the unsigned value in a register by the unsigned value in the specified registeror memory location. The register to be divided depends on the size of the divisor.When dividing a word, the dividend is in the AX register. The instruction stores thequotient in the AL register and the remainder in the AH register.When dividing a doubleword, quadword, or double quadword, the most-significantword of the dividend is in the rDX register and the least-significant word is in the rAXregister. After the division, the instruction stores the quotient in the rAX register andthe remainder in the rDX register.The following table summarizes the action of this instruction:Division Size Dividend Divisor Quotient Remainder Maximum QuotientWord/byte AX reg/mem8 AL AH 255Doubleword/word DX:AX reg/mem16 AX DX 65,535Quadword/doubleword EDX:EAX reg/mem32 EAX EDX 2 32 –1Double quadword/quadwordRDX:RAX reg/mem64 RAX RDX 2 64 –1The instruction truncates non-integral results towards 0 and the remainder is alwaysless than the divisor. An overflow generates a #DE (divide error) exception, ratherthan setting the CF flag.Division by zero generates a divide-by-zero exception.Mnemonic Opcode DescriptionDIV reg/mem8 F6 /6DIV reg/mem16 F7 /6Perform unsigned division of AX by the contents of an 8-bitregister or memory location and store the quotient in AL and theremainder in AH.Perform unsigned division of DX:AX by the contents of a 16-bitregister or memory operand store the quotient in AX and theremainder in DX.140 DIV