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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005Table 3-5.EDX BitCPUID St<strong>and</strong>ard Feature Support (St<strong>and</strong>ard Function 1—EDX) (continued)Feature(feature is supported if bit is set to 1)8 CMPXCHG8B Instruction.9Advanced Programmable Interrupt Controller (APIC). BIOS must enable the local APIC. See thedocumentation for particular implementations of the architecture.10 Reserved.11SYSENTER <strong>and</strong> SYSEXIT <strong>Instructions</strong>. These instructions have different implementations than theSYSCALL <strong>and</strong> SYSRET instructions indicated by bit 11 of extended function 8000_0001h. See “SYSENTER<strong>and</strong> SYSEXIT (Legacy Mode Only)” in <strong>Volume</strong> 2.12 Memory-Type Range Registers (MTRRs). See “Memory-Type Range Registers” in <strong>Volume</strong> 2.13 Page Global Extension. See “Global Pages” in <strong>Volume</strong> 2.14 Machine Check Architecture. See “Machine Check Mechanism” in <strong>Volume</strong> 2.15Conditional Move <strong>Instructions</strong>. Indicates support for conditional move (CMOVcc) general-purposeinstructions, <strong>and</strong>—if the on-chip x87-instruction-unit bit (bit 0) is also set—for the x87 floating-pointconditional move (FCMOVcc) instructions.16 Page Attribute Table (PAT). See “Memory-Type Range Registers” in <strong>Volume</strong> 2.17 Page-Size Extensions (PSE). See“Page-Size Extensions (PSE) Bit” in <strong>Volume</strong> 2.18 Reserved.19CLFLUSH Instruction. Indicates support for the CLFLUSH (writeback, if modified, <strong>and</strong> invalidate) generalpurposeinstruction.20–22 Reserved.23MMX <strong>Instructions</strong>. Indicates support for the integer (MMX) 64-bit media instructions. For details, seeAppendix D, “Instruction Subsets <strong>and</strong> CPUID Feature Sets.”24 FXSAVE <strong>and</strong> FXRSTOR <strong>Instructions</strong>. See “FXSAVE <strong>and</strong> FXRSTOR <strong>Instructions</strong>” in <strong>Volume</strong> 2.2526SSE <strong>Instructions</strong>. Indicates support for the SSE instructions, except that the SSE instructions indicated forthe AMD Extensions to MMX <strong>Instructions</strong> feature (bit 22 of extended function 8000_0001h; see Table 3-7on page 127) are implemented if bit 25 is cleared <strong>and</strong> bit 22 of extended function 8000_0001h is set. Fordetails, see Appendix D, “Instruction Subsets <strong>and</strong> CPUID Feature Sets.”SSE2 Instruction Extensions. Indicates support for the SSE2 instructions. For details, see Appendix D,“Instruction Subsets <strong>and</strong> CPUID Feature Sets.”27 Reserved.28 Hyper-Threading Technology (HTT). (See “Logical Processor Count” on page 122.)29–31 Reserved.124 CPUID

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