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AMD64 Technology 24594 Rev. 3.10 February 2005Initial APIC ID. This field contains the initial value of the processor’s local APICphysical ID register. This value is composed of the Northbridge NodeID (bits 26–24)and the CPU number within the node (bits 31–27). Subsequent writes by software tothe local APIC physical ID register do not change the value of the initial APIC IDfield.Logical Processor Count. The interpretation of the value in the logical processor countfield depends on the value of the core multiprocessing legacy (CMP legacy) bit (ECXbit 1) returned by CPUID extended function 8000_0001h (See Table 3-6). If the valueof the CMP legacy bit is 0, then the value returned for the HTT bit (standard function1, EDX bit 28) (see Table 3-5) indicates the presence of hyperthreading and the valueof the logical processor count field indicates the number of threads for each core on apackage. If the value of the CMP legacy bit is 1, then the value of the HTT bitindicates the presence of multiple cores per package and the value of the logicalprocessor count field indicates the number of cores per package.The logical processor count field is reserved (RAZ) if the HTT bit is 0.The CMP legacy bit can be set for multiple core processors that do not supporthyperthreading. This allows software to detect multiple cores as if they were multiplethreads. This method of detecting multiple cores is discouraged; where possible, newsoftware should use should use extended function 8000_0008h to return the number ofcores per package in ECX[7:0].CLFLUSH Size. This field specifies the size (in quadwords) of the cache line that isflushed by the CLFLUSH instruction. This field is implemented only if the CLFLUSHinstruction is supported. To determine if the CLFLUSH instruction is supported, testthe CLFLUSH instruction bit provided by function 1 feature flags.8-bit Brand ID. The 8-bit brand ID field identifies some AMD64 processors with aunique set of features as a specific brand. The BIOS uses the 8-bit brand ID field toprogram the processor name string that is returned byfunctions 8000_0002h–8000_0004h. If the brand ID field is 0, then the 12-bit brand IDfield (returned in EBX by extended function 8000_0001h) is used to determine theprocessor name string. For more information on the 12-bit brand ID, see “ExtendedFunction 8000_0001h EBX: 12-bit Brand ID” on page 125.For information on using the 8-bit brand ID to program the processor name string, seethe AMD Processor Recognition Application Note, order# 20734.0000_0001h ECX: Standard Feature Support. Standard function 1 returns standard-featurebits in the ECX register. The value of each bit indicates whether support for a specificfeature is present on the processor implementation. If the value of a bit is 1, thefeature is supported. If the value is 0, the feature is not supported. The ECX register is122 CPUID
24594 Rev. 3.10 February 2005 AMD64 Technologyan extension of the EDX register to represent newly introduced standard processorfeatures.Table 3-4 summarizes the standard-feature bits returned in the ECX register forstandard function 1.Table 3-4.ECX Bit0CPUID Standard Feature Support (Standard Function 1—ECX)Feature(feature is supported if bit is set to 1)SSE3 Instructions. Indicates support for the SSE3 instructions. For details, see Appendix D, “InstructionSubsets and CPUID Feature Sets.”1–12 Reserved.13 CMPXCHG16B Instruction.14–31 Reserved.0000_0001h EDX: Standard Feature Support. Standard function 1 returns standard-featurebits in the EDX register. The value of each bit indicates whether support for a specificfeature is present on the processor implementation. If the value of a bit is 1, thefeature is supported. If the value is 0, the feature is not supported.Table 3-5 summarizes the standard-feature bits returned in the EDX register forstandard function 1.Table 3-5.EDX BitCPUID Standard Feature Support (Standard Function 1—EDX)Feature(feature is supported if bit is set to 1)0 On-Chip x87-Instruction Unit.1 Virtual-Mode Extensions. See “Virtual Interrupts” in Volume 2.2 Debugging Extensions. See “Software-Debug Resources” in Volume 2.3 Page-Size Extensions (PSE). See “Page-Size Extensions (PSE) Bit” in Volume 2.4 Time-Stamp Counter. See “Time-Stamp Counter” in Volume 2.5AMD K86 Model-Specific Registers (MSRs), with RDMSR and WRMSR Instructions. See “Model-Specific Registers (MSRs)” in Volume 2.6 Physical-Address Extensions (PAE). See “Physical-Address Extensions (PAE) Bit” in Volume 2.7 Machine Check Exception. See “Handling Machine Check Exceptions” in Volume 2.CPUID 123
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