Volume 3: General-Purpose and System Instructions - Stanford ...

AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsMExceptionInvalid opcode, #UDRealXVirtual8086 Protected Cause of ExceptionXXThe CMPXCHG8B instruction is not supported, as indicated by EDXbit 8 of CPUID standard function 1 or extended function 8000_0001h.XThe CMPXCHG16B instruction is not supported, as indicated by ECXbit 13 of CPUID standard function 1.X X X The operand was a register.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XXThe destination operand was in a non-writable segment.A null data segment was used to reference memory.X The memory operand for CMPXCHG16B was not aligned on a 16-byteboundaryPage fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.116 CMPXCHG8/16B