Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.114 CMPXCHG
24594 Rev. 3.10 February 2005 AMD64 TechnologyCMPXCHG8BCMPXCHG16BCompare and Exchange Eight BytesCompare and Exchange Sixteen BytesCompares the value in the rDX:rAX registers with a 64-bit or 128-bit value in thespecified memory location. If the values are equal, the instruction copies the value inthe rCX:rBX registers to the memory location and sets the zero flag (ZF) of therFLAGS register to 1. Otherwise, it copies the value in memory to the rDX:rAXregisters and clears ZF to 0.If the effective operand size is 16-bit or 32-bit, the CMPXCHG8B instruction is used.This instruction uses the EDX:EAX and ECX:EBX register operands and a 64-bitmemory operand. If the effective operand size is 64-bit, the CMPXCHG16Binstruction is used; this instruction uses RDX:RAX and RCX:RBX register operandsand a 128-bit memory operand.The CMPXCHG8B and CMPXCHG16B instructions support the LOCK prefix. Fordetails about the LOCK prefix, see “Lock Prefix” on page 10.Support for the CMPXCHG8B and CMPXCHG16B instructions depends on theprocessor implementation. To find out if a processor can execute the CMPXCHG8Binstruction, use the CPUID instruction to determine whether EDX bit 8 of CPUIDstandard function 1 or extended function 8000_0001h is set to 1. To find out if aprocessor can execute the CMPXCHG16B instruction, use the CPUID instruction todetermine whether ECX bit 13 of CPUID standard function 1 is set to 1.The memory operand used by CMPXCHG16B must be 16-byte aligned or else ageneral-protection exception is generated.Mnemonic Opcode DescriptionCMPXCHG8B mem64CMPXCHG16B mem128Related InstructionsCMPXCHG0F C7 /1 m640F C7 /1 m128Compare EDX:EAX register to 64-bit memory location. If equal,set the zero flag (ZF) to 1 and copy the ECX:EBX register to thememory location. Otherwise, copy the memory location toEDX:EAX and clear the zero flag.Compare RDX:RAX register to 128-bit memory location. If equal,set the zero flag (ZF) to 1 and copy the RCX:RBX register to thememory location. Otherwise, copy the memory location toRDX:RAX and clear the zero flag.CMPXCHG8/16B 115
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AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination oper<strong>and</strong> was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.114 CMPXCHG
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