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Volume 3: General-Purpose and System Instructions - Stanford ...

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24594 Rev. 3.10 February 2005 AMD64 TechnologyCMOVccConditional MoveConditionally moves a 16-bit, 32-bit, or 64-bit value in memory or a general-purposeregister (second oper<strong>and</strong>) into a register (first oper<strong>and</strong>), depending upon the settingsof condition flags in the rFLAGS register. If the condition is not satisfied, theinstruction has no effect.The mnemonics of CMOVcc instructions denote the condition that must be satisfied.Most assemblers provide instruction mnemonics with A (above) <strong>and</strong> B (below) tags tosupply the semantics for manipulating unsigned integers. Those with G (greater than)<strong>and</strong> L (less than) tags deal with signed integers. Many opcodes may be represented bysynonymous mnemonics. For example, the CMOVL instruction is synonymous with theCMOVNGE instruction <strong>and</strong> denote the instruction with the opcode 0F 4C.Support for CMOVcc instructions depends on the processor implementation. Todetermine whether a processor can perform CMOVcc instructions, use the CPUIDinstruction to determine whether EDX bit 15 of CPUID st<strong>and</strong>ard function 1 orextended function 8000_0001h is set to 1.Mnemonic Opcode DescriptionCMOVO reg16, reg/mem16CMOVO reg32, reg/mem32CMOVO reg64, reg/mem64CMOVNO reg16, reg/mem16CMOVNO reg32, reg/mem32CMOVNO reg64, reg/mem64CMOVB reg16, reg/mem16CMOVB reg32, reg/mem32CMOVB reg64, reg/mem64CMOVC reg16, reg/mem16CMOVC reg32, reg/mem32CMOVC reg64, reg/mem64CMOVNAE reg16, reg/mem16CMOVNAE reg32, reg/mem32CMOVNAE reg64, reg/mem64CMOVNB reg16,reg/mem16CMOVNB reg32,reg/mem32CMOVNB reg64,reg/mem640F 40 /r Move if overflow (OF = 1).0F 41 /r Move if not overflow (OF = 0).0F 42 /r Move if below (CF = 1).0F 42 /r Move if carry (CF = 1).0F 42 /r Move if not above or equal (CF = 1).0F 43 /r Move if not below (CF = 0).CMOVcc 103

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