Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005CLFLUSHCache Line FlushFlushes the cache line specified by the mem8 linear-address. The instruction checksall levels of the cache hierarchy—internal caches and external caches—andinvalidates the cache line in every cache in which it is found. If a cache contains a dirtycopy of the cache line (that is, the cache line is in the modified or owned MOESI state),the line is written back to memory before it is invalidated. The instruction sets thecache-line MOESI state to invalid.The instruction also checks the physical address corresponding to the linear-addressoperand against the processor’s write-combining buffers. If the write-combiningbuffer holds data intended for that physical address, the instruction writes the entirecontents of the buffer to memory. This occurs even though the data is not cached inthe cache hierarchy. In a multiprocessor system, the instruction checks the writecombiningbuffers only on the processor that executed the CLFLUSH instruction.The CLFLUSH instruction is weakly-ordered with respect to other instructions thatoperate on memory. Speculative loads initiated by the processor, or specifiedexplicitly using cache-prefetch instructions, can be reordered around a CLFLUSHinstruction. Such reordering can cause freshly-loaded cache lines to be flushedunintentionally. The only way to avoid this situation is to use the MFENCE instructionto force strong-ordering of the CLFLUSH instruction with respect to other memoryoperations. The LFENCE, SFENCE, and serializing instructions are not ordered withrespect to CLFLUSH.The CLFLUSH instruction behaves like a load instruction with respect to setting thepage-table accessed and dirty bits. That is, it sets the page-table accessed bit to 1, butdoes not set the page-table dirty bit.The CLFLUSH instruction is supported if CPUID standard function 1 sets EDX bit 19.CPUID function 1 returns the CLFLUSH size in EBX bits 23:16. This value reports thesize of a line flushed by CLFLUSH in quadwords. See CPUID for details.The CLFLUSH instruction executes at any privilege level. CLFLUSH performs all thesegmentation and paging checks that a 1-byte read would perform, except that it alsoallows references to execute-only segments.Mnemonic Opcode DescriptionCFLUSH mem8 0F AE /7 flush cache line containing mem8.100 CLFLUSH
24594 Rev. 3.10 February 2005 AMD64 TechnologyRelated InstructionsINVD, WBINVDrFLAGS AffectedNoneExceptionsException (vector) RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The CLFLUSH instruction is not supported, as indicated byEDX bit 19 of CPUID standard function 1.Stack, #SS X X X A memory address exceeded the stack segment limit or wasnon-canonical.General protection, #GP X X XA memory address exceeded a data segment limit or wasnon-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.CLFLUSH 101
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24594 Rev. 3.10 February 2005 AMD64 TechnologyRelated <strong>Instructions</strong>INVD, WBINVDrFLAGS AffectedNoneExceptionsException (vector) RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The CLFLUSH instruction is not supported, as indicated byEDX bit 19 of CPUID st<strong>and</strong>ard function 1.Stack, #SS X X X A memory address exceeded the stack segment limit or wasnon-canonical.<strong>General</strong> protection, #GP X X XA memory address exceeded a data segment limit or wasnon-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.CLFLUSH 101
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