Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005BSRBit Scan ReverseSearches the value in a register or a memory location (second operand) for the mostsignificantset bit. If a set bit is found, the instruction clears the zero flag (ZF) andstores the index of the most-significant set bit in a destination register (first operand).If the second operand contains 0, the instruction sets ZF to 1 and does not change thecontents of the destination register. The bit index is an unsigned offset from bit 0 ofthe searched value.Mnemonic Opcode DescriptionBSR reg16, reg/mem16 0F BD /r Bit scan reverse on the contents of reg/mem16.BSR reg32, reg/mem32 0F BD /r Bit scan reverse on the contents of reg/mem32.BSR reg64, reg/mem64 0F BD /r Bit scan reverse on the contents of reg/mem64.Related InstructionsBSFrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsU U M U U U21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded the data segment limit or was noncanonical.XA null data segment was used to reference memory.76 BSR
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionRealVirtual8086 Protected Cause of ExceptionPage fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.BSR 77
- Page 56 and 57: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 58 and 59: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 60 and 61: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 62 and 63: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 64 and 65: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 66 and 67: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 68 and 69: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 70 and 71: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 72 and 73: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 74 and 75: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 76 and 77: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 78 and 79: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 80 and 81: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 82 and 83: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 84 and 85: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 86 and 87: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 88 and 89: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 90 and 91: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 92 and 93: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 94 and 95: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 96 and 97: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 98 and 99: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 100 and 101: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 102 and 103: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 104 and 105: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 108 and 109: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 110 and 111: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 112 and 113: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 114 and 115: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 116 and 117: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 118 and 119: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 120 and 121: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 122 and 123: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 124 and 125: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 126 and 127: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 128 and 129: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 130 and 131: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 132 and 133: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 134 and 135: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 136 and 137: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 138 and 139: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 140 and 141: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 142 and 143: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 144 and 145: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 146 and 147: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 148 and 149: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 150 and 151: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 152 and 153: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 154 and 155: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionRealVirtual8086 Protected Cause of ExceptionPage fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.BSR 77