Cyclone V SoC FPGA Development Board Reference Manual - Altera

2–46 Chapter 2: Board ComponentsMemoryTable 2–34. QSPI Flash Schematic Signal Names and FunctionsBoardReference (U5)7 QSPI_SS0 A18 3.3-V Chip enable3 QSPI_RESETN — 3.3-V Reset (driven from the MAX V CPLD)EPCQ FlashCFI FlashSchematicSignal NameCyclone V SoC PinNumberI/O StandardDescriptionThe development board supports one 256-Mb serial/quad-serial NOR flash device fornon-volatile storage of the FPGA configuration image. The device connects to theFPGA dedicated interface through the IDTQS3861 device.Table 2–34 lists the EPCQ flash pin assignments, signal names, and functions. Thesignal names and types are relative to the MAX V CPLD 5M2210 System Controller interms of I/O setting and direction. Some pins are used in other interfaces as well dueto functionality sharing.Table 2–35. EPCQ Flash Schematic Signal Names and FunctionsBoardReference (U20)Schematic Signal Name I/O Standard Description16 FPGA_DCLK 3.3-V Clock15 FPGA_AS_DATA0 3.3-V Data bus8 FPGA_AS_DATA1 3.3-V Data bus9 FPGA_AS_DATA2 3.3-V Data bus1 FPGA_AS_DATA3 3.3-V Data bus7 FPGA_NCS0 3.3-V Chip enableThe development board supports a 512-Mb CFI-compatible synchronous flash devicefor non-volatile storage of FPGA configuration data. This device connects to theMAX V CPLD 5M2210 System Controller for FPGA configuration in FPP and PSmodes.This 16-bit data memory interface can sustain burst read operations at up to 52 MHzfor a throughput of 832 Mbps per device. The write performance is 270 µs for a singleword buffer while the erase time is 800 ms for a 128 K array block.Table 2–36 lists the flash pin assignments, signal names, and functions. The signalnames and types are relative to the MAX V CPLD 5M2210 System Controller in termsof I/O setting and direction.Table 2–36. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)BoardReference (U6)Schematic Signal Name I/O Standard DescriptionF6 FLASH_ADVN 1.8-V Address validB4 FLASH_CEN0 1.8-V Chip enableE6 FLASH_CLK 1.8-V ClockF8 FLASH_OEN 1.8-V Output enableCyclone V SoC Development Board November 2013 Altera CorporationReference Manual