Cyclone V SoC FPGA Development Board Reference Manual - Altera

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2–44 Chapter 2: Board ComponentsMemoryTable 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)BoardReferenceSchematicSignal NameCyclone V SoCPin NumberI/O StandardDescriptionK1 DDR3_HPS_ODT H28 1.5-V SSTL Class I On-die termination enableJ3 DDR3_HPS_RASN D30 1.5-V SSTL Class I Row address selectT2 DDR3_HPS_RESETN P30 1.5-V SSTL Class I ResetL3 DDR3_HPS_WEN C28 1.5-V SSTL Class I Write enableL8 DDR3_HPS_ZQ2 — 1.5-V SSTL Class I ZQ impedance calibrationDDR3 x16 (U14)N3 DDR3_HPS_A0 F26 1.5-V SSTL Class I Address busP7 DDR3_HPS_A1 G30 1.5-V SSTL Class I Address busP3 DDR3_HPS_A2 F28 1.5-V SSTL Class I Address busN2 DDR3_HPS_A3 F30 1.5-V SSTL Class I Address busP8 DDR3_HPS_A4 J25 1.5-V SSTL Class I Address busP2 DDR3_HPS_A5 J27 1.5-V SSTL Class I Address busR8 DDR3_HPS_A6 F29 1.5-V SSTL Class I Address busR2 DDR3_HPS_A7 E28 1.5-V SSTL Class I Address busT8 DDR3_HPS_A8 H27 1.5-V SSTL Class I Address busR3 DDR3_HPS_A9 G26 1.5-V SSTL Class I Address busL7 DDR3_HPS_A10 D29 1.5-V SSTL Class I Address busR7 DDR3_HPS_A11 C30 1.5-V SSTL Class I Address busN7 DDR3_HPS_A12 B30 1.5-V SSTL Class I Address busT3 DDR3_HPS_A13 C29 1.5-V SSTL Class I Address busT7 DDR3_HPS_A14 H25 1.5-V SSTL Class I Address busM2 DDR3_HPS_BA0 E29 1.5-V SSTL Class I Bank address busN8 DDR3_HPS_BA1 J24 1.5-V SSTL Class I Bank address busM3 DDR3_HPS_BA2 J23 1.5-V SSTL Class I Bank address busK3 DDR3_HPS_CASN E27 1.5-V SSTL Class I Row address selectK9 DDR3_HPS_CKE L29 1.5-V SSTL Class I Column address selectJ7 DDR3_HPS_CLK_P L23 1.5-V SSTL Class I Differential output clockK7 DDR3_HPS_CLK_N M23 1.5-V SSTL Class I Differential output clockL2 DDR3_HPS_CSN H24 1.5-V SSTL Class I Chip selectE7 DDR3_HPS_DM0 K28 1.5-V SSTL Class I Write mask byte laneD3 DDR3_HPS_DM1 M28 1.5-V SSTL Class I Write mask byte laneH8 DDR3_HPS_DQ0 K23 1.5-V SSTL Class I Data busH7 DDR3_HPS_DQ1 K22 1.5-V SSTL Class I Data busE3 DDR3_HPS_DQ2 H30 1.5-V SSTL Class I Data busH3 DDR3_HPS_DQ3 G28 1.5-V SSTL Class I Data busF7 DDR3_HPS_DQ4 L25 1.5-V SSTL Class I Data busF8 DDR3_HPS_DQ5 L24 1.5-V SSTL Class I Data busG2 DDR3_HPS_DQ6 J30 1.5-V SSTL Class I Data busCyclone V SoC Development Board November 2013 Altera CorporationReference Manual
Chapter 2: Board Components 2–45MemoryTable 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)BoardReferenceSchematicSignal NameF2 DDR3_HPS_DQ7 J29 1.5-V SSTL Class I Data busC8 DDR3_HPS_DQ8 K26 1.5-V SSTL Class I Data busB8 DDR3_HPS_DQ9 L26 1.5-V SSTL Class I Data busD7 DDR3_HPS_DQ10 K29 1.5-V SSTL Class I Data busA7 DDR3_HPS_DQ11 K27 1.5-V SSTL Class I Data busC2 DDR3_HPS_DQ12 M26 1.5-V SSTL Class I Data busC3 DDR3_HPS_DQ13 M27 1.5-V SSTL Class I Data busA3 DDR3_HPS_DQ14 L28 1.5-V SSTL Class I Data busA2 DDR3_HPS_DQ15 M30 1.5-V SSTL Class I Data busG3 DDR3_HPS_DQS_N0 M19B7 DDR3_HPS_DQS_N1 N24F3 DDR3_HPS_DQS_P0 N18QSPI Flash (HPS)Cyclone V SoCPin NumberI/O StandardDifferential 1.5-VSSTL Class IDifferential 1.5-VSSTL Class IDifferential 1.5-VSSTL Class IDescriptionData strobe P byte lane 0Data strobe N byte lane 0Data strobe P byte lane 1C7 DDR3_HPS_DQS_P1 N25Differential 1.5-VSSTL Class IData strobe N byte lane 1K1 DDR3_HPS_ODT H28 1.5-V SSTL Class I On-die termination enableJ3 DDR3_HPS_RASN D30 1.5-V SSTL Class I Row address selectT2 DDR3_HPS_RESETN P30 1.5-V SSTL Class I ResetL3 DDR3_HPS_WEN C28 1.5-V SSTL Class I Write enableL8 DDR3_HPS_ZQ — 1.5-V SSTL Class I ZQ impedance calibrationThe development board supports one 512-Mb quad-SPI (QSPI) flash device for nonvolatilestorage of the HPS boot code, user data, and program. The device connects tothe HPS dedicated interface. The device interface may contain a secondary boot code.This 4-bit data memory interface can sustain burst read operations at up to 108 MHzfor a throughput of 54 MBps. Erase capability is at 4 KB, 64 KB, and 32 MB.Table 2–34 lists the QSPI flash pin assignments, signal names, and functions. Thesignal names and types are relative to the Cyclone V SoC in terms of I/O setting anddirection.Table 2–34. QSPI Flash Schematic Signal Names and FunctionsBoardReference (U5)SchematicSignal NameCyclone V SoC PinNumberI/O Standard16 QSPI_CLK D19 3.3-V Clock15 QSPI_IO0 C20 3.3-V Data bus8 QSPI_IO1 H18 3.3-V Data bus9 QSPI_IO2 A19 3.3-V Data bus1 QSPI_IO3 E19 3.3-V Data busDescriptionNovember 2013 Altera Corporation Cyclone V SoC Development BoardReference Manual
Page 4: ivContentsContentsMemory . . . . .
Page 10 and 11: 2-2 Chapter 2: Board ComponentsBoar
Page 12 and 13: 2-4 Chapter 2: Board ComponentsBoar
Page 14 and 15: 2-6 Chapter 2: Board ComponentsMAX
Page 20 and 21: 2-12 Chapter 2: Board ComponentsFPG
Page 22 and 23: 2-14 Chapter 2: Board ComponentsFPG
Page 24 and 25: 2-16 Chapter 2: Board ComponentsSta
Page 26 and 27: 2-18 Chapter 2: Board ComponentsSet
Page 28 and 29: 2-20 Chapter 2: Board ComponentsGen
Page 30 and 31: 2-22 Chapter 2: Board ComponentsClo
Page 32 and 33: 2-24 Chapter 2: Board ComponentsCom
Page 46 and 47: 2-38 Chapter 2: Board ComponentsMem
Page 58 and 59: 2-50 Chapter 2: Board ComponentsPow
Page 60 and 61: 2-52 Chapter 2: Board ComponentsPow
Page 62 and 63: 3-2 Chapter 3: Board Components Ref
Page 64 and 65: 3-4 Chapter 3: Board Components Ref
Page 66 and 67: Info-2Additional InformationAdditio
Page 68: Info-4Additional InformationAdditio

Cyclone V SoC FPGA Development Board Reference Manual - Altera

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