Cyclone V SoC FPGA Development Board Reference Manual - Altera

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2–38 Chapter 2: Board ComponentsMemory■DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External MemoryInterface Handbook.DDR3 SDRAM (FPGA)The development board supports two 32Mx16x8 DDR3 SDRAM interface for veryhigh-speed sequential memory access. The 32-bit data bus comprises of two ×16devices with a single address or command bus. This interface connects to thededicated HMC I/O banks on the bottom edge of the FPGA.The DDR3 device shipped with this board are running at 400 MHz, for a totaltheoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is800 MHz with a CAS latency of 9.Table 2–32 lists the DDR3 SDRAM pin assignments, signal names, and functions. Thesignal names and types are relative to the Cyclone V SoC in terms of I/O setting anddirection.Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)BoardReferenceSchematicSignal NameCyclone V SoCPin NumberI/O StandardDescriptionDDR3 x16 (U37)N3 DDR3_FPGA_A0 AJ14 1.5-V SSTL Class I Address busP7 DDR3_FPGA_A1 AK14 1.5-V SSTL Class I Address busP3 DDR3_FPGA_A2 AH12 1.5-V SSTL Class I Address busN2 DDR3_FPGA_A3 AJ12 1.5-V SSTL Class I Address busP8 DDR3_FPGA_A4 AG15 1.5-V SSTL Class I Address busP2 DDR3_FPGA_A5 AH15 1.5-V SSTL Class I Address busR8 DDR3_FPGA_A6 AK12 1.5-V SSTL Class I Address busR2 DDR3_FPGA_A7 AK13 1.5-V SSTL Class I Address busT8 DDR3_FPGA_A8 AH13 1.5-V SSTL Class I Address busR3 DDR3_FPGA_A9 AH14 1.5-V SSTL Class I Address busL7 DDR3_FPGA_A10 AJ9 1.5-V SSTL Class I Address busR7 DDR3_FPGA_A11 AK9 1.5-V SSTL Class I Address busN7 DDR3_FPGA_A12 AK7 1.5-V SSTL Class I Address busT3 DDR3_FPGA_A13 AK8 1.5-V SSTL Class I Address busT7 DDR3_FPGA_A14 AG12 1.5-V SSTL Class I Address busM2 DDR3_FPGA_BA0 AH10 1.5-V SSTL Class I Bank address busN8 DDR3_FPGA_BA1 AJ11 1.5-V SSTL Class I Bank address busM3 DDR3_FPGA_BA2 AK11 1.5-V SSTL Class I Bank address busK3 DDR3_FPGA_CASN AH7 1.5-V SSTL Class I Row address selectK9 DDR3_FPGA_CKE AJ21 1.5-V SSTL Class I Column address selectJ7 DDR3_FPGA_CLK_P AA14K7 DDR3_FPGA_CLK_N AA15Differential 1.5-VSSTL Class IDifferential 1.5-VSSTL Class IDifferential output clockDifferential output clockCyclone V SoC Development Board November 2013 Altera CorporationReference Manual
Chapter 2: Board Components 2–39MemoryTable 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)BoardReferenceSchematicSignal NameCyclone V SoCPin NumberL2 DDR3_FPGA_CSN AB15 1.5-V SSTL Class I Chip selectE7 DDR3_FPGA_DM2 AK23 1.5-V SSTL Class I Write mask byte laneD3 DDR3_FPGA_DM3 AJ27 1.5-V SSTL Class I Write mask byte laneE3 DDR3_FPGA_DQ16 AE19 1.5-V SSTL Class I Data busF2 DDR3_FPGA_DQ17 AE18 1.5-V SSTL Class I Data busH8 DDR3_FPGA_DQ18 AG22 1.5-V SSTL Class I Data busF8 DDR3_FPGA_DQ19 AK22 1.5-V SSTL Class I Data busH3 DDR3_FPGA_DQ20 AF21 1.5-V SSTL Class I Data busF7 DDR3_FPGA_DQ21 AF20 1.5-V SSTL Class I Data busG2 DDR3_FPGA_DQ22 AH23 1.5-V SSTL Class I Data busH7 DDR3_FPGA_DQ23 AK24 1.5-V SSTL Class I Data busD7 DDR3_FPGA_DQ24 AF24 1.5-V SSTL Class I Data busC8 DDR3_FPGA_DQ25 AF23 1.5-V SSTL Class I Data busC3 DDR3_FPGA_DQ26 AJ24 1.5-V SSTL Class I Data busC2 DDR3_FPGA_DQ27 AK26 1.5-V SSTL Class I Data busB8 DDR3_FPGA_DQ28 AE23 1.5-V SSTL Class I Data busA7 DDR3_FPGA_DQ29 AE22 1.5-V SSTL Class I Data busA2 DDR3_FPGA_DQ30 AG25 1.5-V SSTL Class I Data busA3 DDR3_FPGA_DQ31 AK27 1.5-V SSTL Class I Data busF3 DDR3_FPGA_DQS_P2 Y17G3 DDR3_FPGA_DQS_N2 AA18C7 DDR3_FPGA_DQS_P3 AC20I/O StandardDifferential 1.5-VSSTL Class IDifferential 1.5-VSSTL Class IDifferential 1.5-VSSTL Class IData strobe P byte lane 2Data strobe N byte lane 2Data strobe P byte lane 3B7 DDR3_FPGA_DQS_N3 AD19Differential 1.5-VSSTL Class IData strobe N byte lane 3K1 DDR3_FPGA_ODT AE16 1.5-V SSTL Class I On-die termination enableJ3 DDR3_FPGA_RASN AH8 1.5-V SSTL Class I Row address selectT2 DDR3_FPGA_RESETN AK21 1.5-V SSTL Class I ResetL3 DDR3_FPGA_WEN AJ6 1.5-V SSTL Class I Write enableL8 DDR3_FPGA_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibrationDDR3 x16 (U38)N3 DDR3_FPGA_A0 AJ14 1.5-V SSTL Class I Address busP7 DDR3_FPGA_A1 AK14 1.5-V SSTL Class I Address busP3 DDR3_FPGA_A2 AH12 1.5-V SSTL Class I Address busN2 DDR3_FPGA_A3 AJ12 1.5-V SSTL Class I Address busP8 DDR3_FPGA_A4 AG15 1.5-V SSTL Class I Address busP2 DDR3_FPGA_A5 AH15 1.5-V SSTL Class I Address busDescriptionNovember 2013 Altera Corporation Cyclone V SoC Development BoardReference Manual
Page 4: ivContentsContentsMemory . . . . .
Page 10 and 11: 2-2 Chapter 2: Board ComponentsBoar
Page 12 and 13: 2-4 Chapter 2: Board ComponentsBoar
Page 14 and 15: 2-6 Chapter 2: Board ComponentsMAX
Page 20 and 21: 2-12 Chapter 2: Board ComponentsFPG
Page 22 and 23: 2-14 Chapter 2: Board ComponentsFPG
Page 24 and 25: 2-16 Chapter 2: Board ComponentsSta
Page 26 and 27: 2-18 Chapter 2: Board ComponentsSet
Page 28 and 29: 2-20 Chapter 2: Board ComponentsGen
Page 30 and 31: 2-22 Chapter 2: Board ComponentsClo
Page 32 and 33: 2-24 Chapter 2: Board ComponentsCom
Page 48 and 49: 2-40 Chapter 2: Board ComponentsMem
Page 58 and 59: 2-50 Chapter 2: Board ComponentsPow
Page 60 and 61: 2-52 Chapter 2: Board ComponentsPow
Page 62 and 63: 3-2 Chapter 3: Board Components Ref
Page 64 and 65: 3-4 Chapter 3: Board Components Ref
Page 66 and 67: Info-2Additional InformationAdditio
Page 68: Info-4Additional InformationAdditio

Cyclone V SoC FPGA Development Board Reference Manual - Altera

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