Cyclone V SoC FPGA Development Board Reference Manual - Altera

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2–34 Chapter 2: Board ComponentsComponents and InterfacesTable 2–23. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)BoardReference (J12)Schematic SignalName143 HSMA_TX_D_P15 B13 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68144 HSMA_RX_D_P15 C13 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69145 HSMA_TX_D_N15 A13 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70146 HSMA_RX_D_N15 B12 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71149 HSMA_TX_D_P16 C12 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72150 HSMA_RX_D_P16 F15 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73151 HSMA_TX_D_N16 B11 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74152 HSMA_RX_D_N16 F14 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75155 HSMA_CLK_OUT_P2 E7 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76156 HSMA_CLK_IN_P2 H15 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77157 HSMA_CLK_OUT_N2 E6 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78158 HSMA_CLK_IN_N2 G15 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79160 HSMA_PRSNTN AD12 2.5-V CMOS HSMC port A presence detectRS-232 UART (HPS)Cyclone V SoCPin NumberI/O StandardDescriptionThe development board supports a UART interface that connects to a mini-USBconnector (J8) using a FT232RQ-REEL USB-to-UART bridge. The maximumsupported rate for this interface is 1 Mbps. Board reference D14 and D15 are theUART LEDs that illuminate to indicate TX and RX activity.Table 2–32 lists the RS-232 UART pin assignments, signal names, and functions. Thesignal names and types are relative to the Cyclone V SoC in terms of I/O setting anddirection.Table 2–24. RS-232 UART Schematic Signal Names and FunctionsBoardReference (U17)SchematicSignal NameCyclone V SoCPin NumberI/O Standard2 UART_TX D24 3.3-V Transmit data30 UART_RX E24 3.3-V Receive data18 RESET_HPS_UART_N — 3.3-V Reset11 POWER_EN — 3.3-V PowerDescriptionCAN Bus (HPS)The development board supports one controller area network (CAN) bus through aDB-9 male connector. The CAN bus is multi-master broadcast serial bus standard forconnecting electronic control units (ECUs). The maximum supported rate for thisinterface is 1 Mbps. This interface uses a dedicated CAN controller inside the HPS. APHY device (U50) is connected in between the HPS and the DB-9 male connector.Cyclone V SoC Development Board November 2013 Altera CorporationReference Manual
Chapter 2: Board Components 2–35Components and InterfacesTable 2–25 lists the PHY device pin assignments, signal names, and functions. Thesignal names and types are relative to the Cyclone V SoC in terms of I/O setting anddirection.Table 2–25. PHY Device Schematic Signal Names and FunctionsBoardReference (U50)Real-Time Clock (HPS)SPI MasterI 2 C InterfaceSchematic SignalNameCyclone V SoCPin NumberI/O Standard7 CANH_P — 3.3-V CAN bus line high6 CANL_N — 3.3-V CAN bus line lowThe HPS system has a battery backed real-time clock (RTC) connected through the I 2 Cinterface. The RTC is implemented using a DS1339 device from MaximSemiconductor. The device has a built-in power sense circuit that detects powerfailures and automatically switches to backup battery supply, maintaining time. Thedevice uses a 357 coin battery with a nominal voltage of 1.55 V. Using typical currentcapacity, the RTC is expected to have 120,000 backup hours. The battery is mountedinside a holder attached to the board to allow battery replacement or removal.Table 2–25 lists the RTC device pin assignments, signal names, and functions. Thesignal names and types are relative to the Cyclone V SoC in terms of I/O setting anddirection.Table 2–26. RTC Device Schematic Signal Names and FunctionsBoardReference (U50)Schematic SignalNameCyclone V SoCPin NumberI/O StandardThe HPS system has a SPI master interface available on the board. This interfaceconnects to the Linear Technology expansion header (J31). This header can power andinterface to most Linear Technology daughter boards such as the included DC934Dual D/A and A/D board.The HPS system has one I 2 C interface for communicating with the on-board andexternal components. The data rate is 50kbps.Table 2–25 lists the I 2 C interface address map.DescriptionDescription16 I2C_SDA_HPS C23 3.3-V Management serial data1 I2C_SCL_HPS D22 3.3-V Management serial clockTable 2–27. I 2 C interface address mapAddress0x680x500x5CDeviceReal-time clockLCDFPGA power monitorNovember 2013 Altera Corporation Cyclone V SoC Development BoardReference Manual
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Cyclone V SoC FPGA Development Board Reference Manual - Altera

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