Cyclone V SoC FPGA Development Board Reference Manual - Altera

Chapter 2: Board Components 2–25Components and InterfacesFigure 2–6 shows the PCI Express reference clock levels.Figure 2–6. PCI Express Reference Clock LevelsVMAX = 1.15 VREFCLK –VCROSS MAX = 550 mVVCROSS MIN = 250 mVREFCLK +VMIN = –0.30 VBy default, the Cyclone V SoC development board is set up for the PCI Expressinterface to use with the Cyclone V SoC device in root-port mode, such as whenplugging in a PCI Express add-in card into the PCI Express socket (J25). In this case,the switching regulator generates and drives the clock to both the Cyclone V SoCdevice and the add-in card.To use the PCI Express interface with the Cyclone V SoC device in end-point mode,for example, with a cable plugged into a PC, you must remove resistors R253, R254,R249, and R251, and install R250 and R252. This resistor change will route the clockfrom the PC directly into the Cyclone V SoC device. You can use a PCI Express gen1x4cable from Samtec (HDR-172378-02-PCIEC) for this connection.1 This cable connects power (3.3 V and 12 V) from the PC to the development board andtherefore the development board's power needs to be isolated to function properly. Toisolate the power, remove the development board's power isolation resistors, R554and R547, located near the PCI Express connector. The ground pin (GND) will stillconnect through the cable as it is required for normal operation.The PCI Express edge connector also has a presence detect feature for themotherboard to determine if a card is installed. A jumper is provided to optionallyconnect PRSNT1n to any of the three PRSNT2n pins found within the x4 connectordefinition. This is to address issues on some PC systems that would base thelink-width capability on the presence detect pins versus a query operation.Table 2–18 summarizes the PCI Express pin assignments. The signal names anddirections are relative to the Cyclone V SoC.Table 2–18. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)BoardReference (J18)Schematic SignalNameI/O StandardCyclone V SoC DevicePin NumberDescriptionA11 PCIE_PERSTN LVTTL AG6 ResetB17 PCIE_PRSNT2N_X1 LVTTL AD29 Presence detect DIP switchB31 PCIE_PRSNT2N_X4 LVTTL A11 Presence detect DIP switchA14 PCIE_REFCLK_SYN_N HCSL W7 Motherboard reference clockA13 PCIE_REFCLK_SYN_P HCSL W8 Motherboard reference clockB5 PCIE_SMCLK LVTTL AE29 SMB clockB6 PCIE_SMDAT LVTTL J14 SMB dataNovember 2013 Altera Corporation Cyclone V SoC Development BoardReference Manual