Cyclone V SoC FPGA Development Board Reference Manual - Altera

2–24 Chapter 2: Board ComponentsComponents and InterfacesTable 2–17. Off-Board Clock OutputsSourceTable 2–17 lists the clock outputs for the development board.Components and InterfacesThis section describes the development board's communication ports and interfacecards relative to the Cyclone V SoC device. The development board supports thefollowing communication ports:■■■■■■■■■■PCI ExpressSchematic SignalNamePCI Express10/100/1000 Ethernet (HPS)10/100 Ethernet (FPGA)HSMCRS-232 Serial UART (HPS)CAN bus (HPS)Real-Time clock (HPS)SPI masterI 2 CSDI videoI/O StandardCyclone V SoCPin NumberDescriptionSamtec HSMC HSMA_CLK_OUT0 2.5-V CMOS A10 FPGA CMOS output (or GPIO)HSMA_CLK_OUT_P1 2.5-V CMOS AJ2Samtec HSMCCMOS outputHSMA_CLK_OUT_N1 2.5-V CMOS AC12HSMA_CLK_OUT_P2 LVDS/2.5V CMOS E7 LVDS output. Can also support 2x CMOSSamtec HSMCHSMA_CLK_OUT_N2 LVDS/2.5V CMOS E6 outputs.PCI Express PCIE_REFCLK_QL0_P HCSL W8HCSL output to the PCI Express socketSocketPCIE_REFCLK_QL0_N HCSL W7The PCI Express interface on the development board supports auto-negotiatingchannel width from ×1 to ×4 as well as the connection speed of Gen1 at 2.5 Gbps/lanefor a maximum of 10 Gbps bandwidth.The PCIE_REFCLK_P/N signal is a 100-MHz differential input that is driven to thedaughter card through the PCI Express edge connector. This signal connects directlyto a Cyclone V SoC REFCLK input pin pair using DC coupling. The I/O standard isHigh-Speed Current Steering Logic (HCSL).Cyclone V SoC Development Board November 2013 Altera CorporationReference Manual