Cyclone V SoC FPGA Development Board Reference Manual - Altera

Chapter 2: Board Components 2–13FPGA ConfigurationThe MAX II CPLD EPM570GF100I5N is dedicated to the on-board USB-Blaster IIfunctionality only, connecting to the USB 2.0 PHY device on one side and drives JTAGsignals out the other side on the GPIO pins. This device's own dedicated JTAGinterface are routed to a small surface-mount header only intended for debugging offirst article prototypes.A USB 2.0 Cypress EZ-USB CY7C68013A device (U51) in a 56-pin VBGA packageinterfaces to a mini-USB connector.Table 2–5 lists the USB 2.0 PHY schematic signal names and their correspondingMAX II CPLD pin numbers.Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)Board Reference(U51)SchematicSignal NameMAX II CPLD PinNumberI/O StandardDescriptionC1 24M_XTALIN — 3.3-V Crystal oscillator inputC2 24M_XTALOUT — 3.3-V Crystal oscillator outputE1 FX2_D_N — 3.3-V USB 2.0 PHY dataE2 FX2_D_P — 3.3-V USB 2.0 PHY dataH7 FX2_FLAGA D1 3.3-V Slave FIFO output statusG7 FX2_FLAGB G1 3.3-V Slave FIFO output statusH8 FX2_FLAGC C1 3.3-V Slave FIFO output statusG6 FX2_PA1 G3 3.3-V USB 2.0 PHY port A interfaceF8 FX2_PA2 B1 3.3-V USB 2.0 PHY port A interfaceF7 FX2_PA3 D2 3.3-V USB 2.0 PHY port A interfaceF6 FX2_PA4 D3 3.3-V USB 2.0 PHY port A interfaceC8 FX2_PA5 K4 3.3-V USB 2.0 PHY port A interfaceC7 FX2_PA6 F2 3.3-V USB 2.0 PHY port A interfaceC6 FX2_PA7 C2 3.3-V USB 2.0 PHY port A interfaceH3 FX2_PB0 G2 3.3-V USB 2.0 PHY port B interfaceF4 FX2_PB1 H8 3.3-V USB 2.0 PHY port B interfaceH4 FX2_PB2 F3 3.3-V USB 2.0 PHY port B interfaceG4 FX2_PB3 J3 3.3-V USB 2.0 PHY port B interfaceH5 FX2_PB4 F1 3.3-V USB 2.0 PHY port B interfaceG5 FX2_PB5 H1 3.3-V USB 2.0 PHY port B interfaceF5 FX2_PB6 H7 3.3-V USB 2.0 PHY port B interfaceH6 FX2_PB7 E1 3.3-V USB 2.0 PHY port B interfaceA8 FX2_PD0 H3 3.3-V USB 2.0 PHY port D interfaceA7 FX2_PD1 H2 3.3-V USB 2.0 PHY port D interfaceB6 FX2_PD2 J2 3.3-V USB 2.0 PHY port D interfaceA6 FX2_PD3 J1 3.3-V USB 2.0 PHY port D interfaceB3 FX2_PD4 J6 3.3-V USB 2.0 PHY port D interfaceA3 FX2_PD5 K3 3.3-V USB 2.0 PHY port D interfaceC3 FX2_PD6 J5 3.3-V USB 2.0 PHY port D interfaceA2 FX2_PD7 K2 3.3-V USB 2.0 PHY port D interfaceNovember 2013 Altera Corporation Cyclone V SoC Development BoardReference Manual