Cyclone V SoC FPGA Development Board Reference Manual - Altera

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2–8 Chapter 2: Board ComponentsMAX V CPLD 5M2210 System ControllerTable 2–4. MAX V CPLD System Controller Device Pin-Out (Part 2 of 4)BoardReference (U19)Schematic Signal Name I/O Standard DescriptionH14 FM_A18 1.8-V FM address busH15 FM_A19 1.8-V FM address busH13 FM_A20 1.8-V FM address busH16 FM_A21 1.8-V FM address busJ13 FM_A22 1.8-V FM address busJ16 FM_A23 1.8-V FM address busK12 FM_A24 1.8-V FM address busM14 FM_A25 1.8-V FM address busN13 FM_A26 1.8-V FM address busJ14 FM_D0 1.8-V FM data busJ15 FM_D1 1.8-V FM data busK16 FM_D2 1.8-V FM data busK13 FM_D3 1.8-V FM data busK15 FM_D4 1.8-V FM data busK14 FM_D5 1.8-V FM data busL16 FM_D6 1.8-V FM data busL11 FM_D7 1.8-V FM data busL15 FM_D8 1.8-V FM data busL12 FM_D9 1.8-V FM data busM16 FM_D10 1.8-V FM data busL13 FM_D11 1.8-V FM data busM15 FM_D12 1.8-V FM data busL14 FM_D13 1.8-V FM data busN16 FM_D14 1.8-V FM data busM13 FM_D15 1.8-V FM data busK1 FPGA_CONF_DONE 2.5-V FPGA configuration done LEDD3 FPGA_CONFIG_D0 2.5-V FPGA configuration dataC2 FPGA_CONFIG_D1 2.5-V FPGA configuration dataC3 FPGA_CONFIG_D2 2.5-V FPGA configuration dataE3 FPGA_CONFIG_D3 2.5-V FPGA configuration dataD2 FPGA_CONFIG_D4 2.5-V FPGA configuration dataE4 FPGA_CONFIG_D5 2.5-V FPGA configuration dataD1 FPGA_CONFIG_D6 2.5-V FPGA configuration dataE5 FPGA_CONFIG_D7 2.5-V FPGA configuration dataF3 FPGA_CONFIG_D8 2.5-V FPGA configuration dataE1 FPGA_CONFIG_D9 2.5-V FPGA configuration dataF4 FPGA_CONFIG_D10 2.5-V FPGA configuration dataF2 FPGA_CONFIG_D11 2.5-V FPGA configuration dataF1 FPGA_CONFIG_D12 2.5-V FPGA configuration dataCyclone V SoC Development Board November 2013 Altera CorporationReference Manual
Chapter 2: Board Components 2–9MAX V CPLD 5M2210 System ControllerTable 2–4. MAX V CPLD System Controller Device Pin-Out (Part 3 of 4)BoardReference (U19)Schematic Signal Name I/O Standard DescriptionF6 FPGA_CONFIG_D13 2.5-V FPGA configuration dataG2 FPGA_CONFIG_D14 2.5-V FPGA configuration dataG3 FPGA_CONFIG_D15 2.5-V FPGA configuration dataN3 FPGA_CVP_CONFDONE 2.5-V FPGA Configuration via Protocol (CvP) doneJ3 FPGA_DCLK 2.5-V FPGA configuration clockN1 FPGA_NCONFIG 2.5-V FPGA configuration activeJ4 FPGA_NSTATUS 2.5-V FPGA configuration readyH1 FPGA_PR_DONE 2.5-V FPGA partial reconfiguration doneP2 FPGA_PR_ERROR 2.5-V FPGA partial reconfiguration errorE2 FPGA_PR_READY 2.5-V FPGA partial reconfiguration readyF5 FPGA_PR_REQUEST 2.5-V FPGA partial reconfiguration requestB11 HPS_RESETN 2.5-V HPS reset push buttonB8 HSMA_PRSNTN 2.5-V HSMC port A presentM1 I2C_SCL_MAX 2.5-V Programmable oscillator I 2 C clockM2 I2C_SDA_MAX 2.5-V Programmable oscillator I 2 C dataL6 JTAG_MAX_TDI 2.5-V JTAG chain data inM5 JTAG_MAX_TDO 2.5-V JTAG chain data outN4 JTAG_MAX_TMS 2.5-V JTAG chain modeP3 JTAG_MUX_TCK 2.5-V JTAG chain clockP11 M570_CLOCK 1.8-V25-MHz clock to embedded USB-Blaster II for sendingFACTORY commandL5 M570_PCIE_JTAG_EN 2.5-V M570 JTAG enable for the embedded USB-Blaster IIH2 MAX_AS_CONF 2.5-VDriven low to enable AS configuration from the EPCQ flashthrough U13 to the FPGAE11 MAX_CONF_DONE 2.5-V Embedded USB-Blaster II configuration done LEDA4 MAX_ERROR 2.5-V FPGA configuration error LEDG4 MAX_FPGA_MISO 2.5-V FPGA to MAX V SPI bus data outputG1 MAX_FPGA_MOSI 2.5-V FPGA to MAX V SPI bus data inputH3 MAX_FPGA_SCK 2.5-V FPGA to MAX V SPI bus clockG5 MAX_FPGA_SSEL 2.5-V FPGA to MAX V SPI bus slave selectA6 MAX_LOAD 2.5-V FPGA configuration active LEDM9 MAX_RESETN 2.5-V MAX V reset push buttonB10 MSEL0 2.5-V FPGA MSEL0 settingB3 MSEL1 2.5-V FPGA MSEL1 settingC10 MSEL2 2.5-V FPGA MSEL2 settingC12 MSEL3 2.5-V FPGA MSEL3 settingC6 MSEL4 2.5-V FPGA MSEL4 settingE10 OVERTEMP 2.5-V Temperature monitor fan enableC7 PCIE_JTAG_EN 2.5-V PCIe JTAG master enableNovember 2013 Altera Corporation Cyclone V SoC Development BoardReference Manual
Page 4: ivContentsContentsMemory . . . . .
Page 10 and 11: 2-2 Chapter 2: Board ComponentsBoar
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Page 14 and 15: 2-6 Chapter 2: Board ComponentsMAX
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