Manufacturing And Reliability Challenges With QFN - SMTA

Who Uses DfR?Military / Avionics / Space Enterprise / Telecom / ATE Consumer / Appliance Industrial / PowerLockheed Martin Cisco Systems Dell Computers General ElectricNorthrop Grumman Huawei (China) Hewlett Packard SiemensGeneral Dynamics Sun Microsystems Apple Emerson ElectricBAE Systems Motorola Fujitsu (Japan) SchlumbergerHoneywell Alcatel-Lucent Samsung (Korea) Ingersoll RandHamilton Sundstrand Juniper Networks LG Electronics (Korea) Danaher MotionThales Communications KLA-Tencor Microsoft OlympusRockwell Collins Xerox Tyco ElectronicsAuto / TransportationPortables General Motors Components MedicalLG Electronics Caterpillar Samsung (Korea) Philips MedicalKyocera Panasonic Automotive Fairchild Semiconductor MedtronicTRW (England) International Rectifier GuidantContract Manufacturers Magna Nvidia Cardinal HealthFlextronics Takata (Japan) Amphenol Beckman CoulterBenchmark Electronics NIC BiotronikGold Circuit Electronics (Taiwan) Materials Cameron HealthDaeduck (Korea) Graftech Cardiac ScienceViasystems (China)Nihon Superior (Japan)And Many More….© 2004 - 20094

Our LocationsMinneapolis OfficeRandy Schuellerrschueller@dfrsolutions.comMichigan OfficeJim McLeishjmcleish@dfrsolutions.comMid-Atlantic Representative:T&M Sales (Tom O’Connor)TaipeiOffice(Fall 2009)Bay Area OfficeJohn McNultyjmcnulty@dfrsolutions.comAustin OfficeCheryl Tulkoffctulkoff@dfrsolutions.comCorporate HeadquartersCollege Park, MDaskdfr@dfrsolutions.com© 2004 - 20095

Knowledge and Education(Website)• Let your staff learnall day / every dayE-LEARNING• Scholarly articles• Technical white papers• Case studies• Reliability calculators• Online presentationsUpdated Website (Launched Aug ’08)© 2004 - 20096

QFN as a ‘Next Generation’Technology• What is ‘Next Generation’ Technology?Materials or designs currentlybeing used, but not widely adopted(especially among hi-rel manufacturers)• Carbon nanotubes are not‘Next Generation’Not used in electronic applications• Ball grid array is not‘Next Generation’Widely adopted© 2004 - 20097

Introduction (cont.)• Why is knowing about ‘NextGeneration’ Technologiesimportant?• These are the technologies thatyou or your supply chain will useto improve your productCheaper, Faster, Stronger,‘Environmentally-Friendly’, etc.• And sooner then you think!© 2004 - 20098

Reliability and Next GenTechnologies• One of the most common drivers for failure isinappropriate adoption of new technologiesThe path from consumer (high volume, short lifetime) tohigh rel is not always clear• Obtaining relevant informationcan be difficultInformation is often segmentedFocus on opportunity, not risks• Can be especially true forcomponent packagingBGA, flip chip, QFN© 2004 - 20099

Component Packaging• Most of us have little influence overcomponent packaging Most devices offer only one or two packagingstyles• Why should you care? Poor understanding of component qualificationprocedures Who tests what and why?© 2004 - 200910

Component Testing• Reliability testing performed by componentmanufacturers is driven by JEDEC JESD22 series (A & B)• Focus is almost entirely on die, packaging, and 1 stlevel interconnections (wire bond, solder bump, etc.)• Only focus on 2 nd level interconnects (solder joints)is JESD22-B113 Cyclic Bend TestDriven by cell phone industryThey have little interest in thermal cycling or vibration!© 2004 - 200911

2 nd Level Interconnect Reliability• IPC has attempted to rectify this throughIPC-9701• Two problems Adopted by OEMs; not by componentmanufacturers Application specific; you have to tell them theapplication (your responsibility, not theirs)• The result An increasing incidence of solder wearout in nextgeneration component packaging© 2004 - 200912

Solder Wearout in Next GenPackagingPerformance Needs• Higher frequencies and data transfer rates Lower resistance-capacitance (RC) constants• Higher densities More inside less• Lower voltage, but higher current Joule heating is I 2 R• Has resulted in less robust package designs© 2004 - 200913

Solder Wearout (cont.)• Elimination of leaded devices Provides lower RC and higher package densities Reduces complianceCycles to failure-40 to 125C QFP: >10,000 BGA: 3,000 to 8,000CSP / Flip Chip:

Solder Wearout (cont.)• Design change: More silicon, less plastic• Increases mismatch in coefficient of thermalexpansion (CTE)BOARD LEVEL ASSEMBLY AND RELIABILITYCONSIDERATIONS FOR QFN TYPE PACKAGES,Ahmer Syed and WonJoon Kang, Amkor Technology.© 2004 - 200915

Industry Response to SJ Wearout?• JEDEC Specification body for component manufacturers• JEDEC JESD47 Guidelines for new component qualification Requires 2300 cycles of 0 to 100C Testing is often done on thin boards• IPC Specification body for electronic OEMs• IPC 9701 Recommends 6000 cycles of 0 to 100C Test boards should be similar thickness asactual design© 2004 - 200917

BIG PROBLEM• JEDEC requirements are 60% less than IPC• Testing on a thin board can extend lifetimes by 2Xto 4X• What does this mean?The components you buy may only survive500 cycles of 0 to 100C• What must you do?Components at risk must be subjected to PoF-basedreliability analysis© 2004 - 200918

Quad Flat Pack No-Lead (QFN)© 2004 - 200919

QFN: What is it?• Quad Flat Pack No Lead or Quad Flat Non-Leaded‘The poor man’s ball grid array’Also known as• Leadframe Chip Scale Package (LF-CSP)• MicroLeadFrame (MLF)• Others (MLP, LPCC, QLP, HVQFN, etc.)• Overmolded leadframe with bond pads exposed on thebottom and arranged alongthe periphery of the packageDeveloped in the early tomid-1990’s by Motorola,Toshiba, Amkor, etc.Standardized by JEDEC/EIAJ inlate-1990’sFastest growing package type© 2004 - 200920

QFN (cont.)• Availability 1 x 2 mm (3 leads) to 14 x 14 mm (120 leads) Dual row may increase I/O count to above 150• Expected to dominate lead counts between 8 to 68Obsolescence of QFP and SOP?• Numerous package outline versions (JEDEC) MO-196 (1998) Available in two and four-sided• Other variationsSingulated (punched) and sawedSingle row and dual row© 2004 - 200921

QFN Advantages: Size and Cost• Smaller, lighter and thinner than comparable leadedpackagesAllows for greater functionality per volume• Reduces costComponent manufacturers: More ICs per frameOEMs: Reduced board size• Attempts to limit the footprint of lower I/O deviceshave previously been stymied for cost reasonsBGA materials and process too expensive© 2004 - 200922

Advantages: Thermal Performance• More direct thermal path with larger areaDie → Die Attach → Thermal Pad →Solder → Board Bond Pad• θJa for the QFN is about half of aleaded counterpart (as per JESD-51)Allows for 2X increase in power dissipation© 2004 - 200924

Advantages: Inductance• At higher operating frequencies, inductance of thegold wire and long lead-frame traces will affectperformance• Inductance of QFN is half its leaded counterpartbecause it eliminates gullwing leads and shortenswire lengthsPopular forRF Designshttp://ap.pennnet.com/display_article/153955/36/ARTCL/none/none/1/The-back-end-process:-Step-9-QFN-Singulation/© 2004 - 200925

QFN: Why Not?• QFN is a ‘next generation’ technology fornon-consumer electronic OEMs due toconcerns with Manufacturability Compatibility with other OEM processes Reliability• Acceptance of this package, especially inlong-life, severe environment, high-relapplications, is currently limited as a result© 2004 - 200926

QFN Manufacturability (BondPads)• Non Solder Mask Defined Pads Preferred (NSMD)Copper etch process has tighter process control than solder mask processMakes for more consistent, strong solder joints since solder bonds to bothtops and sides of pads• Use solder mask defined pads (SMD) with careCan be used to avoid bridging between pads, especially between thermaland signal pads.Pads can grow in size quite a bit based on PCB mfg capabilities• Can lose solder volume through vias in thermal padsMay need to tent vias to keep sufficient paste volumeTenting vias is often not well controlled and can lead to placement andchemical entrapment issuesExercise care with devices placed on opposing side of QFNCan create placement issues if solder “bumps” are created in viasCan create solder short conditions on the opposing device© 2004 - 200927

Bond Pads (cont.)• Extend bond pad 0.2 – 0.3 mm beyondpackage footprintMay or may not solder to cut edgeAllows for better visual inspection• Really need X-ray for best resultsAllows for verification of bridging,adequate solder coverage andvoid percentageNote: Lacking in good criteriafor acceptable voiding© 2004 - 200928

Singulated through sawingSingulated through punching• Concave fillet possible with both sawed or punched QFN Short storage times, active flux• Greater opportunity with punched QFN More copper exposed© 2004 - 200929

Singulated operationTitle: Reliability aspects of electronic devices for advanced requirementsAuthor(s): Florian Schußler, Michael Rosch, Johannes Horber, Klaus FeldmannJournal: Circuit WorldYear: 2008, Volume: 34, Issue: 3, Page: 23 - 30© 2004 - 200930

• Convex or absence of fillet highly likelyEtching of leadframe can prevent pad from reaching edgeof packageEdge of bond pad is not plated for solderability© 2004 - 200931

Title: Reliability study of surface mount printed circuit board assemblies with lead-free solder jointsAuthor(s): Jeffery C.C. Lo, B.F. Jia, Z. Liu, J. Zhu, S.W. Ricky LeeJournal: Soldering & Surface Mount TechnologyYear: 2008, Volume: 20, Issue: 2, Page: 30 - 38© 2004 - 200932

• A large convex fillet is often an indication of issuesPoor wetting under the QFNTilting due to excessive solder paste under the thermal padElevated solder surface tension, from insufficient solderpaste under the thermal pad, pulling the package down© 2004 - 200933

Manufacturability (Rework)• Can be difficult to replace a package and getadequate soldering of thermal / internal pads.Mini-stencils or rebump techniques can be used to getsufficient solder volume• Not directly accessible with soldering iron and wirePortable preheaters used in conjunction with soldering ironcan simplify small scale repair processes• Close proximity with capacitors often requiresadjacent components to be resoldered / replaced aswell© 2004 - 200935

Manufacturability (Stencil Design)• Stencil thickness and aperture design can be crucial formanufacturabilityExcessive amount of paste can inducefloat, lifting the QFN off the boardExcessive voiding can also be inducedthrough inappropriate stencil design• Follow manufacturer’s guidelinesGoal is 2-3 mils of solder thickness• Rules of thumb (thermal pad) Ratio of aperture/pad ~0.5:1 Consider multiple, smaller apertures(avoid large bricks of solder paste) Reduces propensity for solder balling© 2004 - 200936

Manufacturability (cont.)• QFN solder joints are more susceptible to dimensional changes• Case Study: Military supplier experienced solder separation under QFN• QFN supplier admitted that the package was more susceptible tomoisture absorption that initially expectedResulted in transient swelling during reflow solderingInduced vertical lift, causing solder separation• Was not popcorningNo evidence of cracking or delamination in component package© 2004 - 200937

Manufacturability (Board Flexure)• Area array devices are known to have boardflexure limitations For SAC attachment, maximum microstrain canbe as low as 500 ue• QFN has an even lower level of compliance Limited quantifiable knowledge in this area Must be conservative during board build IPC is working on a specification similar to BGAs© 2004 - 200938

Reliability (Thermal Cycling)• Order of magnitude reduction in time tofailure from QFP3X reduction from BGAQFP: >10,000• Driven by die / package ratio 40% die; tf = 8K cycles (-40 / 125C) 75% die; tf = 800 cycles (-40 / 125C)• Driven by size and I/O# 44 I/O; tf = 1500 cycles (-40 / 125C) 56 I/O; tf = 1000 cycles (-40 / 125C)• Very dependent upon solder bond withthermal padBGA: 3,000 to 8,000QFN: 1,000 to 3,000© 2004 - 200939

Thermal Cycling (ConformalCoating)• Care must be taken when using conformal coating over QFNCoating can infiltrate under the QFNSmall standoff height allows coating to cause lift• Hamilton Sundstrand found a significant reduction in time tofailure (-55 / 125C)Uncoated: 2000 to 2500 cyclesCoated: 300 to 700 cycles• Also driven by solder jointsensitivity to tensile stressesDamage evolution is farhigher than for shear stressesWrightson, SMTA Pan Pac 2007© 2004 - 200940

Reliability (Bend Cycling)• Low degree of complianceand large footprint canalso result in issues duringcyclic flexure events• Example: IR tested a5 x 6mm QFN toJEDEC JESD22-B113 Very low beta (~1) Suggests brittle fracture, possible along the interface© 2004 - 200941

Reliability (Dendritic Growth)• Large area, multi-I/O and low standoff can trap fluxunder the QFN• Processes using no-clean flux should be requalifiedParticular configuration could result in weak organic acidconcentrations above maximum (150 – 200 ug/in 2 )• Those processes not using no-clean flux will likelyexperience dendritic growth without modification ofcleaning processChanges in water temperatureChanges in saponifierChanges to impingement jets© 2004 - 200942

Dendritic Growth (cont.)• The electric field strength between adjacent conductors is astrong driver for dendritic growth Voltage / distance• Digital technology typically has a maximum field strength of0.5 V/mil TSSOP80 with 3.3VDC power and 16 mil pitch• Previous generation analog / power technology had a maximumfield strength of 1.6 V/mil SOT23 with 50VDC power and 50 mil pitch• Introduction of QFN has resulted in electric fields as high as3.5 V/mil 24VDC and 16 mil pitch© 2004 - 200943

Dendritic Growth (cont.)• Some component manufacturers are aware of thisissue and separate power and groundLinear Technologies (left) has strong separation power andgroundIntersil (right) has power and ground on adjacent pins© 2004 - 200944

QFN: Risk Mitigation• Assess manufacturabilityDegree of reflow profilingControl of board flexureDOE on stencil designDual row QFN is especially difficult• Assess reliabilityOwnership of 2 nd level interconnectis often lackingExtrapolate to needed field reliabilitySome companies have reballed QFNto deal with concerns© 2004 - 200945