IntelÃ‚Â® Server System Server System "Emerald Ridge ... - CTL

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錯誤 ! 尚未定義樣式。 EPSFunctional Specificationwhen the SEL erasure is completed. This may take several seconds. SEL events that arriveduring the erasure process are queued until the erasure is complete and then committed to theSEL.SEL erasure generates an Event Logging Disabled (Log Area Reset / Cleared offset) sensorevent.3.10 Sensor Data Record (SDR) RepositoryThe BMC implements the sensor data record (SDR) repository as specified in the IntelligentPlatform Management Interface Specification, Version 2.0. The SDR is accessible through theBMC’s in-band and out-of-band interfaces regardless of the system power state The BMCallocates 65,519 bytes of non-volatile storage space for the SDR. See Table 49 for SDRcommand support.3.10.1 SDR Repository ErasureSDR repository erasure is a background process. After initiating erasure with the Clear SDRRepository command, additional Clear SDR Repository commands must be executed to geterasure status and determine when the SDR repository erasure is completed. This may takeseveral seconds. The SDR repository cannot be accessed or modified until the erasure iscompleted.3.10.2 Initialization AgentThe BMC implements the internal sensor initialization agent functionality specified in theIntelligent Platform Management Interface Specification, Version 2.0. When the BMC initializesor on a system boot, it scans the SDR repository and configures the IPMB devices that havemanagement controller records and the Init required bit set in their SDR repository. Thisincludes setting sensor thresholds, enabling or disabling sensor event message scanning, andenabling or disabling sensor event messages.The initialization process causes those IPMB micro-controllers to rearm their event generation.In some cases, this causes a duplicate event to be sent to the BMC. The BMC’s mechanism todetect and delete duplicate events should prevent any duplicate event messages from beinglogged. For details on the initialization agent, refer to the Intelligent Platform ManagementInterface Specification Second Generation v2.0.3.11 Field Replaceable Unit (FRU) Inventory DeviceThe BMC implements the interface for logical FRU inventory devices as specified in theIntelligent Platform Management Interface Specification, Version 2.0. This functionality providescommands used for accessing and managing the FRU inventory information. These commandscan be delivered via all interfaces.The BMC provides FRU device command access to its own FRU device and to the FRUdevices throughout the server. The FRU device ID mapping is defined in the table 7. The BMCcontrols the mapping of the FRU device ID to the physical device.Revision 1.1Intel ® Confidential 21
錯誤 ! 尚未定義樣式。錯誤 ! 尚未定義樣式。 EPS3.11.1 BMC FRU Inventory Area FormatSee the Platform Management FRU Information Storage Definition, Version 1.0.The BMC provides only low-level access to the FRU inventory area storage. It does not validateor interpret the data that is written. This includes the common header area. Applications cannotrelocate or resize any FRU inventory areas.Note: Fields in the internal use area are not for OEM use. Intel reserves the right to relocateand redefine these fields without prior notification. Definition of this area is part of the softwaredesign. The format in the internal use area may vary with different BMC firmware revisions.3.11.2 BMC FRU ID MappingTable 7. FRU Device ID MapFRU DeviceI2C BusI2C AddrFRU Hardware DeviceR/WFRU SizeID(in Bytes)00 1 AAh Baseboard RW 819201 1 ACh IO Riser Board RW 819202 1 A0h Memory Riser Board 1 RW 25603 1 A2h Memory Riser Board 2 RW 25604 1 A4h Memory Riser Board 3 RW 25605 1 A6h Memory Riser Board 4 RW 25606 1 A0h Memory Riser Board 5 RW 25607 1 A2h Memory Riser Board 6 RW 25608 1 A4h Memory Riser Board 7 RW 25609 1 A6h Memory Riser Board 8 RW 2560A 4 AAh Power Distribution Board RW 2560B 4 A0h Power Supply 1 RO 2560C 4 A2h Power Supply 2 RO 2560D 4 A4h Power Supply 3 RO 2560E 4 A8h Power Supply 4 RO 2560F 5 AEh Front Panel Fan Board RW 25610 5 A8h SAS ( Optional) RW 2563.12 Diagnostics and Beep Code GenerationThe BMC may generate beep codes upon detection of failure conditions. Beep codes aresounded each time the problem is discovered (for example, on each power-up attempt), but arenot sounded continuously. Supported codes are listed in Table 8. Each digit in the code isrepresented by a sequence of beeps whose count is equal to the digit.Table 8. BMC Beep CodesCodeReason for Beep1-5-2-1 No CPUs installed or first CPU socket isempty.Associated SensorsCPU Missing SensorSupportedYes22Intel ConfidentialRevision 1.1
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