MODEL DG535 Digital Delay / Pulse Generator - SLAC

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FAST TRANSITION-TIMEMODULESOPTION 04A: 100 ps RISETIMEOPTION 04B: 100 ps FALLTIMEOPTION 04C: BIAS TEEINTRODUCTIONAvailable as options for the Digital Delay /Pulse Generator, these modules will enhance theleading or trailing edge pulse transition times bya factor of 20. Applications include time domainreflectometry measurements, recording the pulseresponse of fast amplifiers, checking high speeddigital circuits or use as a low jitter triggersource in high EMI environments.The devices consist of a step recovery diode andmatching network mounted in an in-line packagewith BNC type connectors. The units provide a fast,low distortion step into a 50 Ω line with adjustableamplitudes from 0.5 V to 2.0 V. There is a fixednegative offset of -0.8 VDC for the fast risetimemodel, and +0.8 VDC for the fast falltime model.These units can provide step amplitudes of up to 3.7V with some increase in distortion, and up to 15 Vwhen used with option 02 (rear panel outputs) andoption 04C (bias tee).OPERATIONFor step amplitudes of less than 3.7 V the fasttransition time units should be attached directly tothe front panel of the DG535.SPECIFICATIONSWhen used on front panel with 50 Ω load.OPTION 04A: FAST RISETIMEOPTION 04B: FAST FALLTIMEOutput Amplitude1 0.5 to 2.0 VDC Output Amplitude1 -0.5 to -2.0 VDCOutput Offset -.8 VDC, typ. Output Offset +0.8 VDC, typ.Transition TimeTransition TimeRise (20/80%) 100 ps, max. Rise (20/80%) 2500 ps, max.Fall (20/80%) 2000 ps, max. Fall (20/80%) 100 ps, max.Pulse AberrationsPulse AberrationsFoot 4%, typ. Foot 4%, typ.Ring ±5%, typ. Ring ±5%, typ.Warranty: One year parts and labor on materials and workmanship.Note1: Amplitudes up to 3.7 Volts are obtainable with some increase in distortion. Amplitudes up to 15 Volts areavailable using DG535 option 02, rear panel ouputs and option 04C, bias tee.42
SETUP FOR OUTPUT STEPS LESSTHAN 2.0 VOLTSOption 04A, Fast Risetime (All front panel outputs)SETUP FOR OUTPUT STEPS UP TO3.7 VOLTSOption 04A, Fast Risetime (All front panel outputs)LOAD= HIGH-Z Internal 50Ω in placeVARiable outputAMPLITUDE +1 to +4V Output step = AMPLITUDE/2OFFSET -1.45 to -1.70 V Adjust for best shapeLOAD = 50ΩVARiable outputsAMPLITUDE = 4.0 VOFFSET = -1.15 VRemoves internal 50ΩOption 04B, Fast Falltime (T0, A, B, C, D only)LOAD = HIGH-Z Internal 50Ω in placeVARiable OutputAMPLITUDE -1 to -4V Output step = AMPLITUDE/2OFFSET +1.45 to +1.70 V Adjust for best shape__ __Option 04B, Fast Falltime (AB, AB, CD, CD)Option 04B, Fast Falltime (T0, A, B, C, D only)LOAD = 50ΩRemoves internal 50ΩVARiable outputsAMPLITUDE = -4.0 VOFFSET = +1.15 V__ __Option 04B, Fast Falltime (AB, AB, CD, CD)LOAD = HIGH-Z Internal 50Ω in placeVARiable OutputAMPLITUDE +1 to +4V Output step = AMPLITUDE/2OFFSET=1.6V-AMPLITUDE Adjust for best shapeLOAD = 50ΩVARiable OutputsAMPLITUDE = 4.0 VOFFSET = 1.15V - AMPLITUDERemoves internal 50ΩOUTPUT STEPS LESS THAN 2.0 VOLTSThe output from the fast transition-time unitswill have a step amplitude of 1/2 of theprogrammed output amplitude from the DG535.The offset, which may be adjusted for the bestpulse shape on the fast transition, will be about -0.8 VDC for the fast risetime unit, and about+0.8 VDC for the fast fall time unit (.ie. 1/2 ofthe programmed offset).The offset is critical to the operation of thedevice: the offset is used to forward bias thestep recovery diode (SRD) prior to the pulseoutput from the DG535. When the pulse fromthe DG535 begins, the stored carriers in theSRD maintain the conduction in the diode,shunting the output pulse to ground. When thestored carriers are depleted (about 3 ns after thestart of the pulse), the diode abruptly stopsconduction, creating a very fast transition timestep at the output.The offset must be increased when the outputamplitude is increased. The offset should be setto about 1.45 v for a 1.0 V amplitude, and toabout 1.70 V for a 4.0 V amplitude from theDG535. The offset may be adjusted for the bestoutput pulse shape. If the offset is set too high,the output step will overshoot: if the offset is toosmall, the output step will undershoot the finalvalue.43OUTPUTS STEPS UP TO 3.7 VOLTSThe step size of the output pulse may be increasedto about 3.7 VDC by changing the outputconfiguration of the DG535. This configuration willincrease the step size and the distortion of the outputpulse.In each of these cases, the offset of the DG535'soutputs may be adjusted for minimum pulsedistortion. Specifying a load impedance of 50 Ω willallow larger pulse amplitudes at the expense ofincreased ringing after the fast transition. Pulseaberrations after the fast transition will be about10%, or about 3x larger than the pulse aberrationswhen a high impedance load is specified.OUTPUT STEPS UP TO 15 VOLTSThe fast rise time (option 04A) and fast fall time(option 04B) units may be used with the highvoltage rear panel outputs (option 02) to generatestep sizes up to 15 V. A bias tee, Option 04C, isrequired for this mode of operation.The high voltage rear panel outputs are ac coupledhence some accommodation must be made toprovide a dc current to forward bias the SRD priorto the output pulse. This current is applied via a biastee (Option 04C) which passes the bias currentthrough an inductor to the diode. The same inductor
Page 1 and 2: MODEL DG535Digital Delay / Pulse Ge
Page 3 and 4: Time Delay vs Repetition 9GPIB PROG
Page 5 and 6: Sheet #2 10 MHz Reference and 80 MH
Page 7 and 8: QUICK START INSTRUCTIONS(1) Make ce
Page 9 and 10: ABRIDGED COMMAND LISTINITIALIZATION
Page 11 and 12: GUIDE TO OPERATIONINTRODUCTIONThe D
Page 13 and 14: is remedied.To use the timebase in
Page 15 and 16: It is often desirable to trigger th
Page 17 and 18: STORE and RECALL MENUSThere are ten
Page 19: other. The pulling of one channel b
Page 22 and 23: 10.0MHz reference is too small or m
Page 24 and 25: incorrect cursor mode will have no
Page 26 and 27: and a trigger input impedance of 50
Page 28 and 29: GPIB PROBLEMSThe first requirement
Page 30 and 31: CALIBRATION MENUSTo access the cali
Page 32 and 33: CIRCUIT DESCRIPTIONThe DG535 has th
Page 34 and 35: threshold, reference oscillator fre
Page 36 and 37: Each of the four delay channels beh
Page 38 and 39: portion of the delay is complete, A
Page 40: +10.000VDC reference is generated o
Page 43 and 44: C 301G 5-00056-512 .1U Cap, Stacked
Page 45 and 46: Q 302C 3-00177-321 2N2222 Transisto
Page 47 and 48: U 109 3-00201-340 MC10H105 Integrat
Page 54: SETUP FOR OUTPUT STEPS UP TO15 VOLT

MODEL DG535 Digital Delay / Pulse Generator - SLAC

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