MODEL DG535 Digital Delay / Pulse Generator - SLAC

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Frequency Synthesizer 24Line Trigger 24Trigger Selection 24Trigger Circuits 25Trigger Sequence 25Overview of the Delay Channels 25Jitter Compensation 26Jitter Precharge and Sample & Hold 26Kickpulse 27The T0 Delay 27Channel A's Digital Delay 27Analog Delays 27Reset Cycle and Status Bits 28Output Drivers 28Offset Control 28Impedance Control 29Gate Output Drivers 29Power Supplies 29Rear Panel Output Drivers 30PARTS LISTSTop PCB 32Bottom PCB 32Front PCB 37Optional Outputs PC Board 37Miscellaneous and Chassis Assembly 38PC LAYOUTTop PCB 39Bottom PCB 40Front PCB 41Optional Outputs PCB 41FAST TRANSITION-TIME MODULES 42SCHEMATIC DIAGRAMS 45Top PCBSheet #1 Microprocessor System, GPIB and Digital I/OSheet #2 Slow Counter/TimersSheet #3 Trigger Status and Reset SequenceSheet #4 Rate GeneratorsSheet #5 Power Supply and Dropout DetectionSheet #6 System Connectors and Polarity ControlBottom PCBSheet #1 Trigger Circuit and Gated 80 MHziii
Sheet #2 10 MHz Reference and 80 MHz PLLSheet #3 Jitter CompensationSheet #4 ECL Counters and Resync CircuitsSheet #5 T0 Analog Delay and Output DriverSheet #6 A Analog Delay and Output DriverSheet #7 B Analog Delay and Output DriverSheet #8 C Analog Delay and Output DriverSheet #9 D Analog Delay and Output DriverSheet #10 AB & CD Gate Output DriversSheet #11 Digital to Analog Converter and MultiplexerSheet #12 Power RegulatorsFront PCBOptional Outputs PCBTable of FiguresFigure - 1 DG535 Rear Panel Page - 2Figure - 2 DG535 Front Panel Page - 3Figure - 3 Maximum Error vs. Time Delay Page - 6Figure - 4 Apparent (Peak To Peak) Jitter and RMS Jitter Page - 7Figure - 5 RMS Jitter Page - 8Figure - 6 DG535 Block Diagram Page - 30Figure - 7 DG535 Timing Diagram Page - 31Figure - 8 Top PC Layout Page - 39Figure - 9 Bottom PC Layout Page - 40Figure - 10Front PC Layout Page - 41Figure - 11Optional Outputs PC Layout Page - 41Figure - 12Fast Transition-Time Modules Page - 42Figure - 13Fast 2 Volt Output Step Page - 44iv
Page 1 and 2: MODEL DG535Digital Delay / Pulse Ge
Page 3: Time Delay vs Repetition 9GPIB PROG
Page 7 and 8: QUICK START INSTRUCTIONS(1) Make ce
Page 9 and 10: ABRIDGED COMMAND LISTINITIALIZATION
Page 11 and 12: GUIDE TO OPERATIONINTRODUCTIONThe D
Page 13 and 14: is remedied.To use the timebase in
Page 15 and 16: It is often desirable to trigger th
Page 17 and 18: STORE and RECALL MENUSThere are ten
Page 19: other. The pulling of one channel b
Page 22 and 23: 10.0MHz reference is too small or m
Page 24 and 25: incorrect cursor mode will have no
Page 26 and 27: and a trigger input impedance of 50
Page 28 and 29: GPIB PROBLEMSThe first requirement
Page 30 and 31: CALIBRATION MENUSTo access the cali
Page 32 and 33: CIRCUIT DESCRIPTIONThe DG535 has th
Page 34 and 35: threshold, reference oscillator fre
Page 36 and 37: Each of the four delay channels beh
Page 38 and 39: portion of the delay is complete, A
Page 40: +10.000VDC reference is generated o
Page 43 and 44: C 301G 5-00056-512 .1U Cap, Stacked
Page 45 and 46: Q 302C 3-00177-321 2N2222 Transisto
Page 47 and 48: U 109 3-00201-340 MC10H105 Integrat
Page 52 and 53: FAST TRANSITION-TIMEMODULESOPTION 0
Page 54:
SETUP FOR OUTPUT STEPS UP TO15 VOLT
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MODEL DG535 Digital Delay / Pulse Generator - SLAC

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