MODEL DG535 Digital Delay / Pulse Generator - SLAC
MODEL DG535 Digital Delay / Pulse Generator - SLAC MODEL DG535 Digital Delay / Pulse Generator - SLAC
portion of the delay is complete, A_CNT and itscomplement are asserted which causes thedifferential pair formed by Q305A and Q306Ato switch the current source away from the OTAand to the capacitor. The OTA is used toprecharge the capacitor to a programmedvoltage: changing the voltage will change theduration of the analog delay. The current sourceis calibrated to charge the capacitor at a rate of100mV/ns, the same rate coefficient that is usedin the jitter compensation circuit. Thecapacitor's voltage is the input to a differentialcomparator formed by Q307A and Q308A. Thejitter voltage is applied to the other side of thecomparator. When the capacitor's voltage equalsthe jitter compensation voltage, the analog delaytimes-out. In this way, the jitter of the triggerwith respect to the internal 80MHz clock iscanceled.The output of the differential comparator (thecollector of Q308A) is applied to the ECL ORgate, 1/4 of U303. The non-inverting output ofthe OR gate is applied to the ECL exclusive ORgate which can invert polarity of the outputpulse. The inverting output of the ECL or gate iswire-ORed with the outputs from the otherchannels. The reset cycle is started when thiswire-ORed signal goes low, indicating that all ofthe delay channels have timed out. During thereset cycle, ECL_HOLD is asserted, holding theoutputs of the ECL OR gate high.RESET CYCLE AND STATUS BITSAn 800ns reset cycle is initiated by TTL_EODwhen all of the delay channels have timed-out.TTL_EOD clocks the 2/2 of U311 high,asserting the GATE pulse. About 200ns later,C301 will be discharged by R302 and P302, andso the output of 1/6 of U312 will go high,asserting the LOAD pulse. About 250ns later,the LOAD pulse is terminated by R304 andP303 charging C303, which brings the output ofthe 2/2 of U312 low. The GATE pulse, and sothe reset cycle, is terminated 350ns later whenC302 is discharged by R303 and P301, resettingthe flip-flop. U311 and U312 are powered froma separate +5.0VDC regulator, U313, to preventnoise from modulating the reset cycle timing.The reset cycle can be initiated by the Z-80 byasserting the CPU_RELOAD signal. CPUreloads are required when the digital delays arechanged, so that the counters will be preset to theirnew values. This signal will reset the 1/2 of U311,presetting the 2/2 of U311 and so start the resetcycle. The 1/2 of U311 is set immediately by theGATE-bar signal, enabling the circuit for the nextCPU_RELOAD. Note that the HOLD pulse, whichmaintains the BNC outputs in their time-out stateduring a normal reset cycle, is disabled during aCPU initiated reset cycle.The GATE and LOAD pulses are used throughoutthe system to preset the ECL, HC, and LSI countersand to precharge the capacitors in the analog delaysand jitter compensation circuits.Three status bits are available to allow the processorknow the state of the delay cycle: BUSY is high ifeither TTL_LATCH is high or if a reset cycle is inprogress. TRIGGERED will be high if a BUSYoccurred since the last polling of this bit.OVERRUN will be set if the unit is triggered whileBUSY with the current timing or reset cycle. BothTRIGGERED and OVERRUN are reset after theyare polled by the Z-80 asserting the FLAG_CLR bit.OUTPUT DRIVERSThe output drivers for each output, T0, A, B, C andD, are essentially the same. Circuit references tochannel A will be used in this description.The outputs of the exclusive-or gate are shifted andattenuated by the resistor network N301A, and usedto drive the bases of the output driver transistorsQ309A and Q310A. The common emitter currentsource is switched between R321A and the outputBNC by these transistors. The amplitude of theoutput pulse is set by the common emitter currentsource, Q316A, which is controlled by the D/Aoutput A_AMP.OFFSET CONTROLThe DC offset voltage of the outputs is controlled bythe bipolar current source formed by Q302, Q303and the op-amps 1/4 and 4/4 of U313. This currentsource is set by the D/A output, OFFSET_CNTL.When sourcing current to the output, only Q303 ison, and the 1/4 of U313 amplifies the differentialvoltage across the 10Ω shunt resistor, R304A. Thissignal is fed-back to the error amplifier, 4/4 ofU313, for comparison to the programmed level,OFFSET_CNTL. The error amplifier drives the base28
of Q303A through the emitter follower Q301Afor improved pulse response at high currents.Q302A is used to sink currents from the outputBNC. The sink current is controlled by feedingback the amplified voltage across the 10Ω shuntresistor, R305A, to the error amplifier, 4/4U313.The offset current is passed to the output viaL301A. This inductor improves the highfrequency response of the current source,maintaining constant current during outputtransitions, and isolating the offset currentsource from the output BNC.IMPEDANCE CONTROLBoth the output pulse driver and the offsetcurrent source require a 50Ω load to workproperly. In some applications the user will notwant to use a 50Ω load, and so, each channelhas a 50Ω load which may be placed on theoutput. This 50Ω load consists of the 45.3Ωresistor, R322A, and the JFET transistor,Q311A, which has about 5Ω of channelresistance when it is turned on by a high levelon A_TERM.The 50Ω load is placed on the output if the userspecifies that there is a high impedance load onthe output. (The load specification is made inthe OUTPUT Menu from the front panel.) If thewrong specification is made then the output willhave 1/2 the programmed amplitude and offset(in the case where two 50Ω loads are on theoutput), or will misbehave altogether (in thecase where no load is on the output).GATE OUTPUT DRIVERSThe Gate Output Drivers are essentially thesame as the output drivers for channels T0, A,B, C and D, except that there are outputs onboth sides of the output current switch formedby Q314 and Q315. This allows thesimultaneous output of the gate pulse and itscomplement for differential pulse applications.The second output requires a second bipolaroffset current source. Both of the offset currentsources are controlled by D/A outputs from theprocessor: these D/A controls are separate (tocompensate for the different input offsetvoltages on the two current sources), but arecontrolled together, i.e., the offset current sourcesare both controlled by the same menu item from thefront panel.POWER SUPPLIESThe unit uses a linear power supply to generate +15,+6.0, +5.2, +5.0, -2.0, -5.2, -6.0, and -15VDC. Theline voltage enters through a power entry module,which provides a fuse and RFI filter. The powerentry module also configures the primary of thepower transformer so that the unit can operate from100, 120, 220 or 240VAC. The secondary voltagesof the power transformer are full-wave rectified byBR601 and BR501 and filtered by C605, C606,C608 and C609 to provide unregulated ±20VDC and±9 VDC.On the "top" PCB, the voltage regulators U501,U503, and U601 provide +5.0, -15, and +15VDC.There is a jumper header in the outputs of each ofthese regulators to allow current measurements to bemade. The +5.0VDC regulator is bypassed by a10Ω, 5Watt resistor to reduce the current in thisregulator. U502, an LM2901 quad comparator, isused to generate active low signals to indicateDROPOUT and RESET. DROPOUT is asserted ifthe unregulated +9VDC drops below 7.5VDC or ifthe unregulated -9VDC goes above -6.8VDC. TheDROPOUT signal generates an interrupt to theprocessor to allow it enough time to store checksumbytes on the instrument settings before power is lost.The RESET signal is asserted for about one secondon power-up (C503 and RN2+R502) or wheneverthe unregulated +9VDC is below 6.8VDC. TheRESET signal is used to reset the microprocessor,and to protect the battery backed-up RAM when thepower is first applied or removed.All of the unregulated voltages and the threeregulated voltages generated on the "top" PCB arepassed down the "bottom" PCB via J7. The voltageregulators on the "bottom" PCB, U902, 903, 909,908 and U907, provide regulated +6.0, +5.2, -2.0, -5.2 and -6.0VDC. All of these regulators, exceptU903 (+5.2VDC), have heat sinks and jumpers intheir outputs (to allow current measurements). The -5.2VDC regulator (U908) is bypassed by a 10Ω,5Watt resistor to reduce the current load in thisregulator. The -2.0VDC regulator, (U909) has a6.8Ω, 5Watt resistor in series with its input toreduce the power dissipated in the regulator. The29
- Page 1 and 2: MODEL DG535Digital Delay / Pulse Ge
- Page 3 and 4: Time Delay vs Repetition 9GPIB PROG
- Page 5 and 6: Sheet #2 10 MHz Reference and 80 MH
- Page 7 and 8: QUICK START INSTRUCTIONS(1) Make ce
- Page 9 and 10: ABRIDGED COMMAND LISTINITIALIZATION
- Page 11 and 12: GUIDE TO OPERATIONINTRODUCTIONThe D
- Page 13 and 14: is remedied.To use the timebase in
- Page 15 and 16: It is often desirable to trigger th
- Page 17 and 18: STORE and RECALL MENUSThere are ten
- Page 19: other. The pulling of one channel b
- Page 22 and 23: 10.0MHz reference is too small or m
- Page 24 and 25: incorrect cursor mode will have no
- Page 26 and 27: and a trigger input impedance of 50
- Page 28 and 29: GPIB PROBLEMSThe first requirement
- Page 30 and 31: CALIBRATION MENUSTo access the cali
- Page 32 and 33: CIRCUIT DESCRIPTIONThe DG535 has th
- Page 34 and 35: threshold, reference oscillator fre
- Page 36 and 37: Each of the four delay channels beh
- Page 40: +10.000VDC reference is generated o
- Page 43 and 44: C 301G 5-00056-512 .1U Cap, Stacked
- Page 45 and 46: Q 302C 3-00177-321 2N2222 Transisto
- Page 47 and 48: U 109 3-00201-340 MC10H105 Integrat
- Page 52 and 53: FAST TRANSITION-TIMEMODULESOPTION 0
- Page 54: SETUP FOR OUTPUT STEPS UP TO15 VOLT
portion of the delay is complete, A_CNT and itscomplement are asserted which causes thedifferential pair formed by Q305A and Q306Ato switch the current source away from the OTAand to the capacitor. The OTA is used toprecharge the capacitor to a programmedvoltage: changing the voltage will change theduration of the analog delay. The current sourceis calibrated to charge the capacitor at a rate of100mV/ns, the same rate coefficient that is usedin the jitter compensation circuit. Thecapacitor's voltage is the input to a differentialcomparator formed by Q307A and Q308A. Thejitter voltage is applied to the other side of thecomparator. When the capacitor's voltage equalsthe jitter compensation voltage, the analog delaytimes-out. In this way, the jitter of the triggerwith respect to the internal 80MHz clock iscanceled.The output of the differential comparator (thecollector of Q308A) is applied to the ECL ORgate, 1/4 of U303. The non-inverting output ofthe OR gate is applied to the ECL exclusive ORgate which can invert polarity of the outputpulse. The inverting output of the ECL or gate iswire-ORed with the outputs from the otherchannels. The reset cycle is started when thiswire-ORed signal goes low, indicating that all ofthe delay channels have timed out. During thereset cycle, ECL_HOLD is asserted, holding theoutputs of the ECL OR gate high.RESET CYCLE AND STATUS BITSAn 800ns reset cycle is initiated by TTL_EODwhen all of the delay channels have timed-out.TTL_EOD clocks the 2/2 of U311 high,asserting the GATE pulse. About 200ns later,C301 will be discharged by R302 and P302, andso the output of 1/6 of U312 will go high,asserting the LOAD pulse. About 250ns later,the LOAD pulse is terminated by R304 andP303 charging C303, which brings the output ofthe 2/2 of U312 low. The GATE pulse, and sothe reset cycle, is terminated 350ns later whenC302 is discharged by R303 and P301, resettingthe flip-flop. U311 and U312 are powered froma separate +5.0VDC regulator, U313, to preventnoise from modulating the reset cycle timing.The reset cycle can be initiated by the Z-80 byasserting the CPU_RELOAD signal. CPUreloads are required when the digital delays arechanged, so that the counters will be preset to theirnew values. This signal will reset the 1/2 of U311,presetting the 2/2 of U311 and so start the resetcycle. The 1/2 of U311 is set immediately by theGATE-bar signal, enabling the circuit for the nextCPU_RELOAD. Note that the HOLD pulse, whichmaintains the BNC outputs in their time-out stateduring a normal reset cycle, is disabled during aCPU initiated reset cycle.The GATE and LOAD pulses are used throughoutthe system to preset the ECL, HC, and LSI countersand to precharge the capacitors in the analog delaysand jitter compensation circuits.Three status bits are available to allow the processorknow the state of the delay cycle: BUSY is high ifeither TTL_LATCH is high or if a reset cycle is inprogress. TRIGGERED will be high if a BUSYoccurred since the last polling of this bit.OVERRUN will be set if the unit is triggered whileBUSY with the current timing or reset cycle. BothTRIGGERED and OVERRUN are reset after theyare polled by the Z-80 asserting the FLAG_CLR bit.OUTPUT DRIVERSThe output drivers for each output, T0, A, B, C andD, are essentially the same. Circuit references tochannel A will be used in this description.The outputs of the exclusive-or gate are shifted andattenuated by the resistor network N301A, and usedto drive the bases of the output driver transistorsQ309A and Q310A. The common emitter currentsource is switched between R321A and the outputBNC by these transistors. The amplitude of theoutput pulse is set by the common emitter currentsource, Q316A, which is controlled by the D/Aoutput A_AMP.OFFSET CONTROLThe DC offset voltage of the outputs is controlled bythe bipolar current source formed by Q302, Q303and the op-amps 1/4 and 4/4 of U313. This currentsource is set by the D/A output, OFFSET_CNTL.When sourcing current to the output, only Q303 ison, and the 1/4 of U313 amplifies the differentialvoltage across the 10Ω shunt resistor, R304A. Thissignal is fed-back to the error amplifier, 4/4 ofU313, for comparison to the programmed level,OFFSET_CNTL. The error amplifier drives the base28
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