MODEL DG535 Digital Delay / Pulse Generator - SLAC

KICKPULSEOTA's (Operational TransconductanceAmplifiers) are used throughout the system toprecharge capacitors when the delay cycle iscomplete. The maximum steady state biascurrent to these devices is only a few milliamps,so, in order to rapidly recharge these capacitors,a "kick pulse" isused to boost the current byseveral milliamps at the start of the reset cycle.This "kick pulse" is generated by differentiatingthe 800 ns GATE pulse, amplifying it with anOTA, and buffering with a Darlington pair.THE T0 DIGITAL DELAYThe T0 output is similar to the A, B, C, and Doutput, except the delay cannot be adjusted.When a trigger is received, 4/4 of U104 gatesthe 80 MHz clock to U201T. The first risingedge of the 80 MHz clock sets Q-bar of 1/2U201T, which clocks 1/2 of U103, asserting theT0-CNT to indicate the completion of the digitalcount for the T0 delay. The analog delay portionof the T0 delay is identical to the analog delaysof the other channels.CHANNEL A's DIGITAL DELAYThe digital delays are essentially identical for allof the channels; the references in thisdescription will be to channel A.When a trigger is received, an 80MHz referenceis provided by the ECL OR Gate, U106, to thetwo-bit ECL counter, U201A. The high bit ofthis counter is shifted to TTL levels by 1/4 ofU203 and passed to the "top" PCB. This bit,"A/4", is used as the clock input to the 4-bitbinary counter U304 (a 74HC191). The high bitof the HC counter, "A/64", is used as a clock tothe uPD8253 LSI counters. The maximum clockfrequency to the HC counter is 20MHz and themaximum clock frequency to the LSI counters is1.25MHz.The quad 1:2 multiplexer, U309, passes the Ainputs to the Y outputs during the count cycle.During the 820ns reset cycle, this multiplexersends the LOAD pulse (at the B input) to theLSI counters' clock inputs to reload the countersfor the next timing cycle.The way in which the LSI counters are used dependson the number of cycles which must be counted. Forvery short delays, the output "A/N" may be presethigh by setting the output of the last LSI counter,U206 pin 17, low. In this case, the LSI counters arenot used in the delay cycle.For delays which require 1 to 32767 ticks of the HCcounter in the delay, the output of the LSI counterwhich is connected to the or-gate is set low,allowing the last LSI counter to count the HC ticks.The last LSI counter's output goes low on theterminal count.For delays which require more than 32767 ticks ofthe HC counter, the LSI counter which is clocked bythe inverted output of the HC counter, isprogrammed to divide by 32768. The next LSIcounter's output will go low after 1 to 65535 ticks ofthe first LSI counter thus gating the HC counter'soutput to the last LSI counter. The last LSI counter'soutput goes low after 1 to 65,535 counts.The output from the HC counter (A/64) and theinverted output from the last LSI counter (A/N) arepassed to the bottom PCB for synchronization to the80MHz reference oscillator. The ECL flip-flop, 1/2U202A, is clocked by A/64; if the D-input (A/N) ishigh (indicating that the LSI count is complete) thenthe Q-bar output of the flip-flop will go low. Thiseliminates the jitter of the LSI counter, as the ECLoutput is synchronous with the HC counter'stransition. The final synchronization is done by the2/2 of U202A. This flip flop is clocked by the ECLoutput of the synchronous two-bit ECL counter(20MHz toggle rate). Its output will change statessynchronously with the first clock input after the Q-bar output of the 1/2 of U202A goes low. Theoutputs of 2/2 of U202A going low signal the end ofthe digital count. The channel will stop counting andthe analog delay for the channel will be started.ANALOG DELAYSThe analog delays for each output, T0, A, B, C andD, are essentially the same. Circuit references tochannel A will be used in this description.The analog delays are controlled by charging acapacitor (C309A) with a constant current source(Q304A). The constant current source, and so thedelay calibration, is controlled by D/A output(A_CAL) from the processor. When the digital27