MODEL DG535 Digital Delay / Pulse Generator - SLAC
MODEL DG535 Digital Delay / Pulse Generator - SLAC MODEL DG535 Digital Delay / Pulse Generator - SLAC
Each of the four delay channels behave like a 37bit presettable synchronous binary ECL counter.Each channel actually consists of a 2 bit ECLcounter (a 10131 dual flip-flop), a 4 bit HCcounter (a 74HC191), and three 16 bit LSIcounters (uPD8253's). To overcome the longpropagation delays in the HC and LSI counters,there are two ECL flip-flops that re-synchronizethe counter output to the 80MHz clock.Throughout the instrument there are manyplaces where signals must be converted betweenECL and HCMOS levels. To convert from ECLto HCMOS, a 10125 Quad ECL to TTLconverter is used, with a resistor pull-up. Toconvert from HCMOS to ECL, a three-resistornetwork is used.Analog time delay circuits provide delays from0 to 12.495ns so that delays may be set with a5ps resolution. These analog delays alsocompensate for the jitter in the digital delayoutput which arises from the uncertainty in thephase of an external trigger with respect to the80MHz internal clock. Without jittercompensation this uncertainty would give rise toa 12.5ns jitter.JITTER COMPENSATIONThe purpose of the jitter compensation circuit isto produce a voltage, which is proportional tothe time between the trigger and a rising edge ofthe 80MHz clock. This voltage is used tomodify the analog delays on each channel so asto eliminate this large component of outputjitter.The jitter voltage is produced by integrating aconstant current source on a capacitor for thetime that the jitter pulse is present. The constantcurrent source, Q113, is controlled by a D/Aoutput from the processor. The D/A voltage,which is stored on C108, is compared to thevoltage across the resistor R137. The correctD/A voltage is determined in final calibration ofthe instrument and is stored in the unit's ROM.A very low leakage current switch formed byQ111 and Q112 is controlled byJITTER_PULSE. While the jitter pulse is on, allof the current is drawn from the integratingcapacitor, C106. The voltage on C106 will bereduced by exactly 100mV per nanosecond ofjitter pulse. The voltage on C106 is buffered byQ109, a J310 FET, level shifted by D102, a 12VZener, to drive the base of the emitter-follower,Q110. The emitter of Q110 is the source of the jittercompensation voltage for all of the analog delaycircuits. The JFET and Zener are biased by theconstant current source, Q116, a JFET run atId=Idss.Small leakage currents can cause the jitter voltage todrift. The dual op-amp, U112, prevents the jittervoltage from drifting so far as to cause a problemwith the analog delay circuits. If the jitter voltagedrifts up beyond the safe limit, 2/2 of U112 willlower the drain voltage to Q109 to stop the drift.(The safe upper limit threshold is reduced during thetiming cycle by the size of the step at the collectorof Q106. In this way, the drift limit circuit is notactive while the timing cycle is not active, allowingthe precharge of the integrating capacitor.) If thejitter voltage drifts down below -7.4VDC, then 1/2of U112 will raise the voltage on the source of Q116and so stop the downward drift.JITTER PRECHARGE AND S&HThree reference voltages are generated by the opamp,1/4 of U312. The input to this circuit is the+10.000VDC reference. The op-amp is configuredwith a gain of -1.07 to produce an output of -10.70VDC. The output is divided to producereference levels of -7.40 and -4.00VDC.The -4.0VDC is the pre-trigger level for the jittervoltage. Before the trigger, ECL_LATCH is low andso Q107 is on, and so its collector is about 3Voltsabove the -15VDC supply. This will provide about1mA to the bias input (pin 16) of the OperationalTransconductance Amplifier, 1/2 U111. The OTAwill source or sink current to the integratingcapacitor to bring the jitter voltage to -4.0VDC.When the unit is triggered, ECL_LATCH goes high,turning off the OTA.The integrating capacitor, C106, needs to be smallso that its voltage may change appreciably duringthe brief jitter pulse. However, small leakagecurrents will rapidly discharge such a smallcapacitor. To eliminate this problem a much largercapacitor, C104, is charged by an OTA , 2/2 ofU111, to provide a charge reservoir. This sampleand hold OTA is active only during the first fewmicroseconds after the trigger since the bias currentto the OTA drops off as C103 discharges.26
KICKPULSEOTA's (Operational TransconductanceAmplifiers) are used throughout the system toprecharge capacitors when the delay cycle iscomplete. The maximum steady state biascurrent to these devices is only a few milliamps,so, in order to rapidly recharge these capacitors,a "kick pulse" isused to boost the current byseveral milliamps at the start of the reset cycle.This "kick pulse" is generated by differentiatingthe 800 ns GATE pulse, amplifying it with anOTA, and buffering with a Darlington pair.THE T0 DIGITAL DELAYThe T0 output is similar to the A, B, C, and Doutput, except the delay cannot be adjusted.When a trigger is received, 4/4 of U104 gatesthe 80 MHz clock to U201T. The first risingedge of the 80 MHz clock sets Q-bar of 1/2U201T, which clocks 1/2 of U103, asserting theT0-CNT to indicate the completion of the digitalcount for the T0 delay. The analog delay portionof the T0 delay is identical to the analog delaysof the other channels.CHANNEL A's DIGITAL DELAYThe digital delays are essentially identical for allof the channels; the references in thisdescription will be to channel A.When a trigger is received, an 80MHz referenceis provided by the ECL OR Gate, U106, to thetwo-bit ECL counter, U201A. The high bit ofthis counter is shifted to TTL levels by 1/4 ofU203 and passed to the "top" PCB. This bit,"A/4", is used as the clock input to the 4-bitbinary counter U304 (a 74HC191). The high bitof the HC counter, "A/64", is used as a clock tothe uPD8253 LSI counters. The maximum clockfrequency to the HC counter is 20MHz and themaximum clock frequency to the LSI counters is1.25MHz.The quad 1:2 multiplexer, U309, passes the Ainputs to the Y outputs during the count cycle.During the 820ns reset cycle, this multiplexersends the LOAD pulse (at the B input) to theLSI counters' clock inputs to reload the countersfor the next timing cycle.The way in which the LSI counters are used dependson the number of cycles which must be counted. Forvery short delays, the output "A/N" may be presethigh by setting the output of the last LSI counter,U206 pin 17, low. In this case, the LSI counters arenot used in the delay cycle.For delays which require 1 to 32767 ticks of the HCcounter in the delay, the output of the LSI counterwhich is connected to the or-gate is set low,allowing the last LSI counter to count the HC ticks.The last LSI counter's output goes low on theterminal count.For delays which require more than 32767 ticks ofthe HC counter, the LSI counter which is clocked bythe inverted output of the HC counter, isprogrammed to divide by 32768. The next LSIcounter's output will go low after 1 to 65535 ticks ofthe first LSI counter thus gating the HC counter'soutput to the last LSI counter. The last LSI counter'soutput goes low after 1 to 65,535 counts.The output from the HC counter (A/64) and theinverted output from the last LSI counter (A/N) arepassed to the bottom PCB for synchronization to the80MHz reference oscillator. The ECL flip-flop, 1/2U202A, is clocked by A/64; if the D-input (A/N) ishigh (indicating that the LSI count is complete) thenthe Q-bar output of the flip-flop will go low. Thiseliminates the jitter of the LSI counter, as the ECLoutput is synchronous with the HC counter'stransition. The final synchronization is done by the2/2 of U202A. This flip flop is clocked by the ECLoutput of the synchronous two-bit ECL counter(20MHz toggle rate). Its output will change statessynchronously with the first clock input after the Q-bar output of the 1/2 of U202A goes low. Theoutputs of 2/2 of U202A going low signal the end ofthe digital count. The channel will stop counting andthe analog delay for the channel will be started.ANALOG DELAYSThe analog delays for each output, T0, A, B, C andD, are essentially the same. Circuit references tochannel A will be used in this description.The analog delays are controlled by charging acapacitor (C309A) with a constant current source(Q304A). The constant current source, and so thedelay calibration, is controlled by D/A output(A_CAL) from the processor. When the digital27
- Page 1 and 2: MODEL DG535Digital Delay / Pulse Ge
- Page 3 and 4: Time Delay vs Repetition 9GPIB PROG
- Page 5 and 6: Sheet #2 10 MHz Reference and 80 MH
- Page 7 and 8: QUICK START INSTRUCTIONS(1) Make ce
- Page 9 and 10: ABRIDGED COMMAND LISTINITIALIZATION
- Page 11 and 12: GUIDE TO OPERATIONINTRODUCTIONThe D
- Page 13 and 14: is remedied.To use the timebase in
- Page 15 and 16: It is often desirable to trigger th
- Page 17 and 18: STORE and RECALL MENUSThere are ten
- Page 19: other. The pulling of one channel b
- Page 22 and 23: 10.0MHz reference is too small or m
- Page 24 and 25: incorrect cursor mode will have no
- Page 26 and 27: and a trigger input impedance of 50
- Page 28 and 29: GPIB PROBLEMSThe first requirement
- Page 30 and 31: CALIBRATION MENUSTo access the cali
- Page 32 and 33: CIRCUIT DESCRIPTIONThe DG535 has th
- Page 34 and 35: threshold, reference oscillator fre
- Page 38 and 39: portion of the delay is complete, A
- Page 40: +10.000VDC reference is generated o
- Page 43 and 44: C 301G 5-00056-512 .1U Cap, Stacked
- Page 45 and 46: Q 302C 3-00177-321 2N2222 Transisto
- Page 47 and 48: U 109 3-00201-340 MC10H105 Integrat
- Page 52 and 53: FAST TRANSITION-TIMEMODULESOPTION 0
- Page 54: SETUP FOR OUTPUT STEPS UP TO15 VOLT
Each of the four delay channels behave like a 37bit presettable synchronous binary ECL counter.Each channel actually consists of a 2 bit ECLcounter (a 10131 dual flip-flop), a 4 bit HCcounter (a 74HC191), and three 16 bit LSIcounters (uPD8253's). To overcome the longpropagation delays in the HC and LSI counters,there are two ECL flip-flops that re-synchronizethe counter output to the 80MHz clock.Throughout the instrument there are manyplaces where signals must be converted betweenECL and HCMOS levels. To convert from ECLto HCMOS, a 10125 Quad ECL to TTLconverter is used, with a resistor pull-up. Toconvert from HCMOS to ECL, a three-resistornetwork is used.Analog time delay circuits provide delays from0 to 12.495ns so that delays may be set with a5ps resolution. These analog delays alsocompensate for the jitter in the digital delayoutput which arises from the uncertainty in thephase of an external trigger with respect to the80MHz internal clock. Without jittercompensation this uncertainty would give rise toa 12.5ns jitter.JITTER COMPENSATIONThe purpose of the jitter compensation circuit isto produce a voltage, which is proportional tothe time between the trigger and a rising edge ofthe 80MHz clock. This voltage is used tomodify the analog delays on each channel so asto eliminate this large component of outputjitter.The jitter voltage is produced by integrating aconstant current source on a capacitor for thetime that the jitter pulse is present. The constantcurrent source, Q113, is controlled by a D/Aoutput from the processor. The D/A voltage,which is stored on C108, is compared to thevoltage across the resistor R137. The correctD/A voltage is determined in final calibration ofthe instrument and is stored in the unit's ROM.A very low leakage current switch formed byQ111 and Q112 is controlled byJITTER_PULSE. While the jitter pulse is on, allof the current is drawn from the integratingcapacitor, C106. The voltage on C106 will bereduced by exactly 100mV per nanosecond ofjitter pulse. The voltage on C106 is buffered byQ109, a J310 FET, level shifted by D102, a 12VZener, to drive the base of the emitter-follower,Q110. The emitter of Q110 is the source of the jittercompensation voltage for all of the analog delaycircuits. The JFET and Zener are biased by theconstant current source, Q116, a JFET run atId=Idss.Small leakage currents can cause the jitter voltage todrift. The dual op-amp, U112, prevents the jittervoltage from drifting so far as to cause a problemwith the analog delay circuits. If the jitter voltagedrifts up beyond the safe limit, 2/2 of U112 willlower the drain voltage to Q109 to stop the drift.(The safe upper limit threshold is reduced during thetiming cycle by the size of the step at the collectorof Q106. In this way, the drift limit circuit is notactive while the timing cycle is not active, allowingthe precharge of the integrating capacitor.) If thejitter voltage drifts down below -7.4VDC, then 1/2of U112 will raise the voltage on the source of Q116and so stop the downward drift.JITTER PRECHARGE AND S&HThree reference voltages are generated by the opamp,1/4 of U312. The input to this circuit is the+10.000VDC reference. The op-amp is configuredwith a gain of -1.07 to produce an output of -10.70VDC. The output is divided to producereference levels of -7.40 and -4.00VDC.The -4.0VDC is the pre-trigger level for the jittervoltage. Before the trigger, ECL_LATCH is low andso Q107 is on, and so its collector is about 3Voltsabove the -15VDC supply. This will provide about1mA to the bias input (pin 16) of the OperationalTransconductance Amplifier, 1/2 U111. The OTAwill source or sink current to the integratingcapacitor to bring the jitter voltage to -4.0VDC.When the unit is triggered, ECL_LATCH goes high,turning off the OTA.The integrating capacitor, C106, needs to be smallso that its voltage may change appreciably duringthe brief jitter pulse. However, small leakagecurrents will rapidly discharge such a smallcapacitor. To eliminate this problem a much largercapacitor, C104, is charged by an OTA , 2/2 ofU111, to provide a charge reservoir. This sampleand hold OTA is active only during the first fewmicroseconds after the trigger since the bias currentto the OTA drops off as C103 discharges.26
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