25-Gb/s Optical Transceiver System
25-Gb/s Optical Transceiver System
25-Gb/s Optical Transceiver System
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<strong>25</strong>-<strong>Gb</strong>/s <strong>Optical</strong> <strong>Transceiver</strong> <strong>System</strong>• 4-channel BIST system using FPGA <strong>Transceiver</strong> Evaluation Kit FPGA has a maximum 8.5<strong>Gb</strong>ps speed <strong>Transceiver</strong>s1. Design a <strong>Transceiver</strong> block• Using Quartus II to design 4 channel transceiver blocks (6.<strong>25</strong><strong>Gb</strong>ps x 4 = <strong>25</strong><strong>Gb</strong>ps)• For 6.<strong>25</strong><strong>Gb</strong>ps, we should use 32:1 SerDes system.2. Design a Pattern Generator• PRBS7,15,31 pattern generator and high-speed clock(10101010…)• Error injection function3. Design a Bit Error Checker• Applying Error checker function• Error count summation1
Low-power TDC designabPFDArbiterdelaydelayDirection1bitMUXstartstopDLL1GHz clkDLL128 Vernier delay lines& SamplerDecoderOutput 7bitabPFDArbiterdelaydelayDirection1bitMUXstartstopDFF1GHz clkDFF1nsDLLslowDFFDLLfast128 Vernier delay lines& SamplerDecoderOutput 7bit300umDLLsSampler&Delaylines270umDecoderLow-power DLL TDC- 3.9ps resolution- ±500ps input range- Power : 4.6mW- Area : 270um x 300umConventional DLL TDC- 3.9ps resolution- ±500ps input range- Power : 10.4mW- Area : 270um x 300um2
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