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section - Bitsavers

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PHASE LOCKED LOOP APPLICATIONSbaud or bits per second, or 150Hz) and twice the inputfrequency (about 2200Hz). The free-running frequencyshould be adjusted (with R 1) so that the dc voltage level atthe output is the same as that at pin 6 of the loop. Theoutput signal can now be made logic compatible byconnecting a voltage comparator between the ,output andpin 6.The input connection is typical for cases where a dc voltageis present at the source and, therefore, a direct connectionis not desirable. Both input terminals are returned toground with identical resistors (in this case, the values arechosen to achieve a 600n input impedance.)FSK DECODER WITH EXPANDED565 OUTPUT VOLTAGE RANGEV,:z+14VFor best operation, the free-running veo frequency shouldbe adjusted so that the output voltage (corresponding tothe input frequencies of 1070Hz and 1270Hz swingsequally to both sides of the reference voltage at pin 6. Thiscan be easily done by adjusting the center frequency of theveo so that the output signal of the 5710 comparator hasa 50% duty cycle. It is usually necessary to decouple pin 6with a large capacitor connected to the positive supply inorder to obtai n a stable reference voltage for the 5710comparator.Figure 8-54 shows the output of the 5710 comparator andthe output of the 565 phase locked loop after the filter atrates of 100,200 and 300 baud, respectively.100 BAUD FSK DECODINGINPUTo---}r-.--f---IOUTPUTFigure 8-53A more sophisticated approach primarily useful for narrowfrequency deviations is shown in Figure 8-53. Here, aconstant current is injected into pin 8 by means oftransistor 01. This has the effect of decreasing the lockrange and increasing the output voltage sensitivity to theinput frequency shift. The basis for this scheme is the factthat the output voltage (control voltage for VeO) controlsonly the current through R 1, while the current through 01remains constant. Thus, if most of the capacitor chargingcurrent is due to 01, the current variation due to R 1 willbe a small percentage of the total charging current and,consequently, the total frequency deviation of the veowill be limited to a small percentage of the centerfrequency. A 0.25mfd loop filter capacitor gives approximately30% overshoot on the output pulse, as seen in theaccompanying photographs.The output is then filtered with a two-stage Re ladderfilter with a band edge chosen to be approximately 800Hz(approximately half-way between the maximum keyingrate of 150Hz and twice the carrier frequency). Thenumber of stages on the filter can be more or lessdepending on the degree of uncertainty allowable in thecomparator output pulse. Two small capacitors (typically0.001 mfd) are connected between pins 8 and 7 of the 565and across the input of the comparator to avoid possibleoscillation problems.Figure 8-54a200 BAUD FSK DECODINGFigure 8-54b300 BAUD FSK DECODIN.GF~gure 8-54c57

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