section - Bitsavers

PHASE LOCKED LOOP APPLICATIONSSpecial layout precautions are required to be sure that nohigh frequency coupling occurs via grounds or powersupply lines. The circuit is adjusted by trimming the 562VCO trimmer capacitor until the beat note present at testpoint 1 has the same frequency as f m throughout thedeviation range (f m can be deviated by hand or very slowly,say, at a 1 Hz rate, to observe that the beat note does notbreak up during sweep. If the beat note is lost at eitherextreme, adjust the VCO trimmer. If the full deviationcannot be obtained, decrease the 562 low pass filtercapacitor sl ightly. Connect a cou nter to the output to besure the loop is locked to fR + fm and not fR - fm (unlessthe latter is desired).Naturally, the component values given may be altered forother applications. Note that as fm is made a smaller andsmaller percentage of the total output frequency, itbecomes difficult to prevent locking in the fR - fm modesince the 562 lock range will likely include both fR - fmand fR + f m . However, if fm is made too large a portion ofthe output frequency, then overall stability suffers unlessf m is also qu ite precise.PHASE LOCKED FSK DEMODULATORS (5608,565)FSK refers to data transmission by means of a carrierwhich is shifted between two preset frequencies. Thisfrequency shift is usually accomplished by driving a VCOwith the binary data signal so that the two resultingfrequencies correspond to the "0" and "1" states(commonly called space and mark) of the binary datasignal.The 560B phase locked loop can be used as a recelvmgconverter to demodulate FSK audio tones and to provide ashifting dc voltage to initiate mark or space code elements.The PLL can replace the bulky audio filters andundependable relay circuits previously used for thisapplication. Connection of the 560B PLL as a FSKdemodulator is illustrated in Figure 8-51.The system functions by locking-on and tracking theoutput frequency of the receiver. The demodulatorfrequency shift appears at pin 9 as a direct-current voltageof about 60mV amplitude and must be amplified andsignal-conditioned to interface with the printer. The inputvoltage at pin 12 should be from 30mV to 2V peak-to-peak,square or sine wave. Pin 10, the de-emphasis terminal, isused for bandshaping. The capacitor connected betweenthis terminal and ground bypasses unwanted highfrequency noise to ground. Pin 9 is the output (approximately60mV dc) which is amplified, conditioned and fedto a voltage comparator amplifier (N5710) to provide theproper voltages for interfacing with the printer. Thisspecific circuit was designed to match the Bell 103C and103D Data Phones. When modifying this circuit toaccommodate other systems, maintain the resistance toground from pin 9 at approximately 15Q. Pins 3 and 2 arethe connections for the external capacitor that determinethe free-running frequency of the VCO. The 0.33MF· valueindicated provides a VCO frequency, f o ' of approximately1060Hz. The value of the timing capacitor can beCo = 300pFcalculated by use of the following equation:where fo is in Hertz.The output has a swing of 2V peak-to-peak, over a 0 to 600baud input FSK rate, with less than 10% jitter at thecomparator output. The circuit is operative over atemperature range of 0° to 75 0 C with a total drift ofapproximately 1 OOmV over the temperature range.A simple scheme using the 565 to receive FSK signals of1070Hz and 1270Hz is shown in Figure 8-52. As the signalappears at the input, the loop locks to the input frequencyand tracks it between the two frequencies with acorresponding dc shift at the output.FSK DECODER USING THE 565FSK DEMODULATOR USING 560810K10KL......;.-+---------+----o-5VFigure 8-52OUTPUTr----"."IIr-+--+---+--......... --o-6VFigure 8-51The loop filter capacitor C2 is chosen to set the properovershoot on the output and a three-stage RC ladder filteris used to remove the sum frequency component. Theband edge of the ladder filter is chosen to be approximatelyhalf-way between the maximum keying rate (30056