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PHASE LOCKED LOOP APPLICATIONSTwo events must occur before an output is given. First, theloop portion of the 567 must achieve lock. Second, theoutput capacitor C3 must charge sufficiently to activatethe output stage. For minimum response time, these eventsmust be as brief as possible.As previously discussed, the lock time of a loop can beminimized by reducing the response time of the low passfilter. Thus, C2 must be as small as possible. However, C2also controls the bandwidth. Therefore, the response timeis an inverse function of bandwidth as shown by Figure8-41, reprinted from the 567 data sheet. The upper curvedenotes the expected worst-case response time when thebandwidth is controlled solely by C2 and the inputamplitude is 200mV rms or greater. The response time isgiven in cycles of center frequency. For example, a 2%bandwidth at a center frequency of 1000 cycles can requireas long as 280 cycles (280ms) to lock when the initialphase relationship is at its worst. Figure 8-42 gives atypical distribution of response time versus input phase.Note that, assuming random initial input phase, only30/180 = 1/6 of the time will the lock-up time be longerthan half the worst case lock-up time. Figure 8-43 showssome actual measurements of lock-up time for a set-uphaving a worst case lock-up time of 27 cycles and a bestcaselock-up time of four input cycles.LOCK-UP TIME VARIATION DUETO RANDOM INITIAL PHASEGREATEST NUMBER OF CYCLES BEFORE OUTPUT100050040030020010050403020101.0\..'\.."\.. I\.'\ , ,,~1\ ,"""I\.'\..r- BANDWIDTH LlMIHD :>-\BANDWOOTH LIM IT'D BY C, _EXTERNAL RESISTOR2I TNrUjC ).'\.'"3 4 5 10 20 30 40 50BANDWIDTH (% of fO)Figure 8-41LOCK-UP TIME VS INITIAL PHASE100Figure 8-43The lower curve on the graph shows the worst-case lock-uptime when the loop gain is reduced as a means of reducingthe bandwidth (see data sheet, Alternate Method ofBandwidth Reduction). The value of C2 required for thisminimum response time isIt is important to note that noise immunity and rejection ofout-band tones suffer somewhat when this minimum value(C2) of C2 is used so that response time is gained at theirexpense. Except at very low input levels, input amplitudehas only a minor effect on the lock-up time-usuallynegligible in comparison to the variation caused by inputphase.J.1F.8.6.4.2oo~\\""!30'",!60 !90~--- ....INITIAL PHASE DIFFERENCE (tPj - 90)Figure 8-42 .'150-'180Lock-up transients can be displayed on a two-channel scopewith ease. Figure 8-44 shows the display which results.The top trace shows the square wave which either gates theinput generator signal off and on (or shifts the frequency inand out of the band if you have a generator which has afrequency control input only). The lower trace shows thevoltage at pin 2, the low pass filter voltage. The inputfrequency is offset slightly from the center frequency sothat the locked and unlocked voltage are different. It isapparent that, while the C2 decay during unlock is alwaysthe same, the lock transient is different each time. This isbecause the turn-on repetition rate is such that a differentinitial phase relationship occurs with each appearance ofthe in-band signal. It is tempting to adjust the repetitionrate so that a fast, constant lock-up transient is displayed.However, in doing a favorable initial phase is created that is45
PHASE LOCKED LOOP APPLICATIONSnot present in actual operation. On the contrary, it is mostrealistic to adjust the repetition rate so that the longestlock-up time is displayed, such as the fifth lock transientshows. Once this display is achieved, the effect of variousadjustments in C2 or input amplitude is seen. However,the repetition rate must be readjusted for worst-caselock-up after each such change.TONE DECODER LOCK-UP TRANSIENTIi OUTSIDE CAPTURE RANGEIi -INSIDE CAPTURE - RANGE -'\'~:~ ~',\~'RRO",OCTAG' \ 'HORT ' \ CONG(PIN 2) LOCKUP LOCK UPTIMEFigure 8-44EFFECT OF THRESHOLD VOLTAGE (V t )ADJUSTMENT ON TONE DECODERTURN-ON AND TURN-OFF DELAYLOCKIVq ----hV t ----IIII:rn .I~ ~RN-ONDELAYLOCKV q___ "'\III---...I IFigure 8-45aUNLOCK1--..lIUNLOCKIIII-------""tIIm ______....!.:--I~RN-ONDELAYFigure 8-45bTIME~RN-OFFI~ TUDELAYI-.IIhURN-OHDELAY46Once lock is achieved, the quadrature phase detectoroutput at pin 1 is integrated by C3 to extract the dccomponent. As C3 charges from its quiescent value V q(see Figure 8-45) to its final value (V q - f::,.V), it passesthrough the output stage threshdld, turning it on. Thetotal voltage change is a function of input amplitude.Since the unadjusted Vq is very close (within 50mV) to V t ,the output stage turns on very soon after lock. Only a smallfraction of the output stage time constant (r = 4700C3)expires before V t is crossed so that C3 does not greatlyinfluence the response time. However, as shown in Figure8-45a, the turn-off delay time can be quite long when C3is large. Figure 8-45b shows how desensitizing the outputstage by connecting a high-value resistor between pin 1 andpin 4 (plus supply) can equalize the turn-on and turn-offtime. If turn-off delay is important in the overall responsetime, then desensitizing can reduce the total delay.But why not make C3 very small so that these delays canbe totally neglected? The problem here is that the GPDoutput has a large twice-center-frequency component thatmust be filtered out. Also, noise, outband signals anddifference frequencies formed by close out-band frequenciesbeating with the VCO frequency appear at theGPD output. All these must be attenuated by C3 or theoutput stage will chatter on and off as the threshold isapproached. The more noisy the input signal and the largerthe near-band signals, the greater C3 must be to rejectthem. Thus, there is a complicated relationship betweenthe input spectrum and the size of C3. What must be done,then, is to make C3 more than sufficient for properoperation (no false outputs or missed signals) under actualoperating conditions and then reduce its value in smallsteps until either the required response time is obtained oroperation becomes unsatisfactory.In setting up the tone decoder for maximum speed, it isbest to proceed as follows:a.)b.)c.)After the center frequency has been set, adjustC2 to give the desired bandwidth or, if thegraph of response time in cycles (Figure 8-43)suggests that worst case lock-up time will betoo long, incorporate the loop gain reductionscheme as an alternate means of bandwidthreduction. (Page 8 of 567 data sheet.)Check lock-up time by observing the waveformat pin 2 while pulsing the input signal on andoff (or in and out of the band when a FMgenerator is used). Adjust repetition rate toreveal worst lock-up time.Starting with a large value of C3 (say 10 C2),reduce it as much as possible in steps whilemonitoring the output to be certain that nofalse outputs or missed signals occur. The fullinput spectrum should be used for this test.Ignore brief transients or chatter during turnonand turn-off as they can be eliminated withthe chatter prevention feedback techniquedescribed in the data sheet.
Page 2 and 3: TABLE OF CONTENTSSECTION TITLE PAGE
Page 4: SECTIONINTRODUCTIONPHASE LOCKED LOO
Page 7 and 8: USER'S QUICK-LOOK GUIDE TO SIGNETIC
Page 10: SECTIONTHE PHASE LOCKED LOOP PRINCI
Page 13 and 14: PHASE LOCKED LOOP APPLICATIONSIt is
Page 15 and 16: PHASE LOCKED LOOP APPLICATIONSROOT
Page 17 and 18: PHASE LOCKED LOOP APPLICATIONSINTEG
Page 19 and 20: ~PHASE LOCKED LOOP APPLICATIONSFUNC
Page 21 and 22: PHASE LOCKED LOOP APPLICATIONSFREQU
Page 24 and 25: PHASE LOCKED LOOP APPLICATIONSGENER
Page 26 and 27: PHASE LOCKED LOOP APPLICATIONSPROBA
Page 28 and 29: ~PHASE LOCKED LOOP APPLICATIONSCapt
Page 30 and 31: PHASE LOCKED LOOP APPLICATIONSTRANS
Page 32 and 33: PHASE LOCKED LOOP APPLICATIONSThe V
Page 34 and 35: PHASE LOCKED LOOP APPLICATIONSINTER
Page 36 and 37: PHASE LOCKED LOOP APPLICATIONSIt is
Page 38 and 39: PHASE LOCKED LOOP APPLICATIONSWhen
Page 40 and 41: PHASE LOCKED LOOP APPLICATIONSSIMPL
Page 42 and 43: PHASE LOCKED LOOP APPLICATIONSSCHEM
Page 44 and 45: PHASE LOCKED LOOP APPLICATIONSNARRO
Page 48: PHASE LOCKED LOOP APPLICATIONSd.)e.
Page 52 and 53: PHASE LOCKED LOOP APPLICATIONSFM IF
Page 54 and 55: PHASE LOCKED LOOP APPLICATIONSPHASE
Page 56 and 57: PHASE LOCKED LOOP APPLICATIONSTRANS
Page 58 and 59: PHASE LOCKED LOOP APPLICATIONSbaud
Page 60 and 61: PHASE LOCKED LOOP APPLICATIONSFigur
Page 62 and 63: PHASE LOCKED LOOP APPLICATIONSinput
Page 64 and 65: PHASE LOCKED LOOP APPLICATIONfTRIAN
Page 66 and 67: PHASE LOCKED LOOP APPLICATIONSRF-FM
Page 68 and 69: PHASE LOCKED LOOP APPLICATIONSVHF O
Page 70 and 71: PHASE LOCKED LOOP APPLICATIONSPRECI
Page 72 and 73: PHASE LOCKED LOOP APPLICATIONSFSK D
Page 74 and 75: PHASE LOCKED LOOP APPLICATIONSThe c
Page 76 and 77: PHASE LOCKED LOOP APPLICATIONSFLUTT
Page 78 and 79: PHASE LOCKED LOOP APPLICATIONSSALES
Page 80 and 81: PHASE LOCKED LOOP APPLICATIONSINTER

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