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PHASE LOCKED LOOP APPLICATIONSWhen operated from dual symmetrical supplies, the squarewave on pin 4 will swing between a low level of slightly(0.2V) below ground to a high level of one diode voltagedrop (O.7V) below positive supply. The triangle waveform on pin 9 is approximately centered between positiveand negative supply and has an amplitude of 2V withsupply voltages of ±5V. The amplitude of the trianglewaveform is directly proportional to the supply voltages.The phase detector is again of the doubly-balancedmodulator type. Transistors 020 and 024 form the signalinput stage, and must be biased externally. If dualsymmetrical supplies are used, it is simplest to bias 020and 024 through external resistors to ground. Theswitching stage 018, 019, 022 and 023 is driven from theSchmitt trigger via pin 5 and Dll. Diodes D12 and D13limit the phase detector output, and differential amplifier026 and 027 provides increased loop gain.The loop low pass filter is formed with an externalcapacitor (connected to pin 7) and the collector resistanceR24 (typically 3.6r2). The voltage on pin 7 becomes theerror voltage which is then connected back to the controlvoltage terminal of the VCO (base of 01). Pin 6 isconnected to a tap on the bias resistor string and providesa reference voltage which is nominally equal to the outputvoltage on pin 7. This allows differential stages to be bothbiased and driven by connecting them to pins 6 and 7.The free-running center frequency of the 565 is adjustedby means of R 1 and Cl and is given approximately by1.2f ~-o4R1ClWhen the phase comparator is in the limiting mode(Vin ~ 200mV p-p), the lock range can be calculated fromthe expression:2wL = 2KoKdAOdThe lock range for the 565 then becomes:to each side of the center frequency, or a total range of:16f o2fL :::: -- HzVccThe capture range, over which the loop can acquire lockwith the input signal is given approximately by:where W L is the one-sided lock rangeand T is the time constant of the loop filterT = RC2with R = 3.6kr2.This can be written as:to each side of the center frequency or a total capturerange of:fc '" ~ J1T321TfOTV ccThis approximation works well for narrow capture ranges(fc = 1/3fL) but becomes too large as the limiting case isapproached (fc = f L ).where Ko is the VCO conversion gain, Kd is the phasedetector gain factor, A is the amplifier gain and Bd is themaximum phase error over which the loop can remain inlock.DETAILED DESCRIPTION OF 56650f oFor the 565: Ko =Vccradians/sec/volt(where fo is the free-running frequency of the VCO andV cc is the total supply voltage applied to the circuit.)Kd1.41TA 1.4°d1T2volts/radianradiansThe 566 is the voltage controlled oscillator portion of the565. The basic die is the same as that of the 565; modifiedmetalization is used to bring out only the VCO. The 566circuit diagram is shown in Figure 8-31. Transistor 018has been a buffered triangle waveform output. (The trianglewaveform is available at capacitor Cl also, but any currentdrawn from pin 7 will alter the duty cycle and frequency.)The square wave output is available from 019 by pin 4. Thecircuit will operate at frequencies up to 1 MHz and may beprogrammed by the voltage applied on the control terminal(pin 5), current injected into pin 6 or the value of theexternal resistor and capacitor (R 1 and C 1).37
PHASE LOCKED LOOP APPLICATIONSSCHEMATIC DIAGRAM OF 566+vl R1~(EXT) 6I5VCo-........ --C8~----~-'--------~--~------~--1---~------1-~V+Rg~------~---------+---+------~------~~--~~------~~----~--o1GNDCURRENT SOURCE VCo SCHMITT TRIGGERFigure 8-31DETAILED DESCRIPTION OF 567The 567 is a PLL designed specifically for frequencysensing or tone decoding. Like the 561, the 567 has acontrolled oscillator, a phase detector and a secondauxiliary or quadrature phase detector. In addition,however, it contains a power output stage which is drivendirectly by the quadrature phase detector output. Duringlock, the quadrature phase detector drives the outputstage on, so the device functions as a tone decoder orfrequency relay. The tone decoder center frequency andbandwidth are specified by the center frequency andcapture range of the loop portion. Since a tone decoder,by definition, responds to a stable frequency, the lock ortracking range is relatively unimportant except as it limitsthe maximum attainable capture range.The current controlled oscillator is shown in simplifiedform in Figure 8-32. It provides both a square waveoutput and a quadrature output. The control current Icsweeps the oscillator ±7% of the center frequency, which isset by external components R 1 and C1. It operates asfollows:Transistors Q1 through Q6 form a flip-flop which canswitch pin 5 between Vbe and V+ - Vbe. Thus, the R1C1network is driven from a square wave of V+ - 2V bepeak-to-peak volts. On the positive portion of the squarewave, Cl is charged through R 1 until V 1 is reached. Acomparator circuit driven from Cl at pin 6 then supplies apulse which resets the flip-flop so that pin 5 switches toVbe and Cl is discharged until V2 is reached. A secondcomparator then supplies a pulse which sets the flip-flopand Cl resumes charging.38
Page 2 and 3: TABLE OF CONTENTSSECTION TITLE PAGE
Page 4: SECTIONINTRODUCTIONPHASE LOCKED LOO
Page 7 and 8: USER'S QUICK-LOOK GUIDE TO SIGNETIC
Page 10: SECTIONTHE PHASE LOCKED LOOP PRINCI
Page 13 and 14: PHASE LOCKED LOOP APPLICATIONSIt is
Page 15 and 16: PHASE LOCKED LOOP APPLICATIONSROOT
Page 17 and 18: PHASE LOCKED LOOP APPLICATIONSINTEG
Page 19 and 20: ~PHASE LOCKED LOOP APPLICATIONSFUNC
Page 21 and 22: PHASE LOCKED LOOP APPLICATIONSFREQU
Page 24 and 25: PHASE LOCKED LOOP APPLICATIONSGENER
Page 26 and 27: PHASE LOCKED LOOP APPLICATIONSPROBA
Page 28 and 29: ~PHASE LOCKED LOOP APPLICATIONSCapt
Page 30 and 31: PHASE LOCKED LOOP APPLICATIONSTRANS
Page 32 and 33: PHASE LOCKED LOOP APPLICATIONSThe V
Page 34 and 35: PHASE LOCKED LOOP APPLICATIONSINTER
Page 36 and 37: PHASE LOCKED LOOP APPLICATIONSIt is
Page 40 and 41: PHASE LOCKED LOOP APPLICATIONSSIMPL
Page 42 and 43: PHASE LOCKED LOOP APPLICATIONSSCHEM
Page 44 and 45: PHASE LOCKED LOOP APPLICATIONSNARRO
Page 46 and 47: PHASE LOCKED LOOP APPLICATIONSTwo e
Page 48: PHASE LOCKED LOOP APPLICATIONSd.)e.
Page 52 and 53: PHASE LOCKED LOOP APPLICATIONSFM IF
Page 54 and 55: PHASE LOCKED LOOP APPLICATIONSPHASE
Page 56 and 57: PHASE LOCKED LOOP APPLICATIONSTRANS
Page 58 and 59: PHASE LOCKED LOOP APPLICATIONSbaud
Page 60 and 61: PHASE LOCKED LOOP APPLICATIONSFigur
Page 62 and 63: PHASE LOCKED LOOP APPLICATIONSinput
Page 64 and 65: PHASE LOCKED LOOP APPLICATIONfTRIAN
Page 66 and 67: PHASE LOCKED LOOP APPLICATIONSRF-FM
Page 68 and 69: PHASE LOCKED LOOP APPLICATIONSVHF O
Page 70 and 71: PHASE LOCKED LOOP APPLICATIONSPRECI
Page 72 and 73: PHASE LOCKED LOOP APPLICATIONSFSK D
Page 74 and 75: PHASE LOCKED LOOP APPLICATIONSThe c
Page 76 and 77: PHASE LOCKED LOOP APPLICATIONSFLUTT
Page 78 and 79: PHASE LOCKED LOOP APPLICATIONSSALES
Page 80 and 81: PHASE LOCKED LOOP APPLICATIONSINTER

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