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PHASE LOCKED LOOP APPLICATIONSINTERFACINGConnection of the Signetics 560B and 561 B phase lockedloops to external input and output circuitry is readilyaccomplished; however, as with any electrical system, thereare voltage, current and impedance limitations that must beconsidered.The inputs of the phase comparators in the 560B, 561 Band562B and the AM detector in the 561 B are biased internallyfrom a +4 volt supply; therefore, the input signals must becapacitively coupled to the PLL to avoid interfering withthis bias. These coupling capacitors should be selected togive negligible phase shift at the input frequency andimpedance of the PLL. (The capacitive impedance at theoperating frequency should be as small as possible,compared to the input resistance of the PLL.)VCO OUTPUT INTERFACING+18V +18V16560B4Oo6Vp-p+605VREFJLJLOo6V5 :..ruLp-p+605V REFFigure 8-22a Figure 8-22bThe input resistance of the phase comparator is 2000nsingle-ended, and 4000n when differentially connected.The input resistance of the AM detector is 3000n. Thesignal input to the phase comparator may be applieddifferentially if there is a common mode noise problem;however, in most applications, a single-ended input will besatisfactory. When inputs are not used differentially, theunused input may be ac-coupled to ground to double thephase detector gain at low input amplitudes.+12VFigure 8-22cThe amplitude of the input signal should be adjusted togive optimum results with the PLL. Signals of less than0.2mV rms may have an unsatisfactory signal-to-noiseratio; signals exceeding 25mV rms will have reduced AMrejection (less than 30dB). The AM detector will handleinput signals up to 200mV peak-to-peak without excessivedistortion, and will handle up to 2V peak-to-peak wheredistortion is not a factor.Figure 8-22dInterfacing of the available outputs is best described byreferring to the following diagrams. Figure 8-22 showsthe PLL VCO output as a clock circuit for logic pulsesynchronization. Figures 8-22a and 8-22b show the 560Band 561 B, respectively, connected directly to the clockcircuit; however, this configuration may be limited by lowvoltage and the possibility of too large a capacitive loadswamping the oscillator. Figures 8-22c and 8-22d showthe PLL clock output for the 560B and 561B, respectively,using the 5710 Voltage Comparator as a buffer amplifier toprovide an output voltage swing suitable for driving logiccircuits. The power supply for circuits utilizing the 5710 issplit (+12 and -6V dc).In Figure 8-23a the 560B is a FM demodulator usedfor the detection of audio information on frequencymodulated carriers. Since the lower frequency limit of thistype of information is approximately 1 Hz, capacitivecoupling may be used. However, in some applications wherecarrier shifts occur at an extremely slow rate, directcoupling from the output to load is necessary. Figure8-23b shows an alternate FM detector output configurationwhich should be used if a different output is desirable.In this case, the output is removed at pins 14 and 15. Thesepins are the terminals of the low pass filter and are in theline containing the demodulated signal. The signal level(single-ended) is about one-sixth of that at pin 9 so thatadditional amplification may be required.33
PHASE LOCKED LOOP APPLICATIONSFM DETECTOR INTERFACINGDETECTOR INTERFACING (NE561B ONL V)+1av+1a1-----.--1 ~AUDIO15K OUTPUTDE-EMPHASISCAPACITORFigure 8-23aFigure 8-24a+1avOUTPUT LOWPILLOW-PASS PASS FILTERFILTER (IF REO'Dj....----, r-----1INPUT o--j 13NE5608NE561BIII~III":' IIIIIIIIIIIIOUTPUTFigure 8-23bFigure 8-24bAdditional receiving modes are illustrated in Figure 8-24for the 561 B only. Figure 8-24a shows the 561 B outputwhen used as an AM detector; note the straight capacitivecoupling. Figure 8-24b shows the 561 B used as acontinuous wave detector. Since this version of the circuitis for the detection of ew or AM signals, external circuitrymust be incorporated for use with ew inputs. With a ew. input applied, there will be a dc shift at the output of theAM detector, pin 1. This shift is small compared to the nosignaldc level and may be difficult to detect in relation topower supply voltage changes. Therefore, a reference mustbe generated to track any power supply voltage variationsand to compensate for internal PLL thermal drift. This isbest accomplished by simulating a portion of the PLLinternal structure. The 2N3565 npn transistor is used as aconstant-current source. Its reference voltage is obtainedfrom an internal PLL bias source at pins 12 and 13, withthe current level established by the 6.8K resistor. The 6.2Kresistor and the 2.5K potentiometer simulate the PLLoutput resistance. The differential amplifier, composed oftwo 2N3638 pnp transistors, amplifies the dc output andallows it to drive a npn transistor referenced to ground.This type of circuit may also be used as a tone detector orto sense that the PLL is locked to an incoming signal.The 562 phase locked loop is especially designed forutilizing the output of the veo. In this configuration, anamplifier-buffer has been added to the veo to providedifferential square wave outputs with a 4.5V amplitude(see block diagram Figure 8-25). This facilitates theutilization of the frequency stabilized veo as a timing orclocking signal. The outputs (pins 3 and 4) are emitterfollowersand have no internal load resistors; therefore,external 3K to 12K n load resistors are required.SIGNALINPUTSBLOCK DIAGRAM OF 562BLOW-PASSFILTERFigure 8-25DE·EMPHASIS34
Page 2 and 3: TABLE OF CONTENTSSECTION TITLE PAGE
Page 4: SECTIONINTRODUCTIONPHASE LOCKED LOO
Page 7 and 8: USER'S QUICK-LOOK GUIDE TO SIGNETIC
Page 10: SECTIONTHE PHASE LOCKED LOOP PRINCI
Page 13 and 14: PHASE LOCKED LOOP APPLICATIONSIt is
Page 15 and 16: PHASE LOCKED LOOP APPLICATIONSROOT
Page 17 and 18: PHASE LOCKED LOOP APPLICATIONSINTEG
Page 19 and 20: ~PHASE LOCKED LOOP APPLICATIONSFUNC
Page 21 and 22: PHASE LOCKED LOOP APPLICATIONSFREQU
Page 24 and 25: PHASE LOCKED LOOP APPLICATIONSGENER
Page 26 and 27: PHASE LOCKED LOOP APPLICATIONSPROBA
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Page 30 and 31: PHASE LOCKED LOOP APPLICATIONSTRANS
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