section - Bitsavers

PHASE LOCKED LOOP APPLICATIONSINTERFACINGConnection of the Signetics 560B and 561 B phase lockedloops to external input and output circuitry is readilyaccomplished; however, as with any electrical system, thereare voltage, current and impedance limitations that must beconsidered.The inputs of the phase comparators in the 560B, 561 Band562B and the AM detector in the 561 B are biased internallyfrom a +4 volt supply; therefore, the input signals must becapacitively coupled to the PLL to avoid interfering withthis bias. These coupling capacitors should be selected togive negligible phase shift at the input frequency andimpedance of the PLL. (The capacitive impedance at theoperating frequency should be as small as possible,compared to the input resistance of the PLL.)VCO OUTPUT INTERFACING+18V +18V16560B4Oo6Vp-p+605VREFJLJLOo6V5 :..ruLp-p+605V REFFigure 8-22a Figure 8-22bThe input resistance of the phase comparator is 2000nsingle-ended, and 4000n when differentially connected.The input resistance of the AM detector is 3000n. Thesignal input to the phase comparator may be applieddifferentially if there is a common mode noise problem;however, in most applications, a single-ended input will besatisfactory. When inputs are not used differentially, theunused input may be ac-coupled to ground to double thephase detector gain at low input amplitudes.+12VFigure 8-22cThe amplitude of the input signal should be adjusted togive optimum results with the PLL. Signals of less than0.2mV rms may have an unsatisfactory signal-to-noiseratio; signals exceeding 25mV rms will have reduced AMrejection (less than 30dB). The AM detector will handleinput signals up to 200mV peak-to-peak without excessivedistortion, and will handle up to 2V peak-to-peak wheredistortion is not a factor.Figure 8-22dInterfacing of the available outputs is best described byreferring to the following diagrams. Figure 8-22 showsthe PLL VCO output as a clock circuit for logic pulsesynchronization. Figures 8-22a and 8-22b show the 560Band 561 B, respectively, connected directly to the clockcircuit; however, this configuration may be limited by lowvoltage and the possibility of too large a capacitive loadswamping the oscillator. Figures 8-22c and 8-22d showthe PLL clock output for the 560B and 561B, respectively,using the 5710 Voltage Comparator as a buffer amplifier toprovide an output voltage swing suitable for driving logiccircuits. The power supply for circuits utilizing the 5710 issplit (+12 and -6V dc).In Figure 8-23a the 560B is a FM demodulator usedfor the detection of audio information on frequencymodulated carriers. Since the lower frequency limit of thistype of information is approximately 1 Hz, capacitivecoupling may be used. However, in some applications wherecarrier shifts occur at an extremely slow rate, directcoupling from the output to load is necessary. Figure8-23b shows an alternate FM detector output configurationwhich should be used if a different output is desirable.In this case, the output is removed at pins 14 and 15. Thesepins are the terminals of the low pass filter and are in theline containing the demodulated signal. The signal level(single-ended) is about one-sixth of that at pin 9 so thatadditional amplification may be required.33