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PHASE LOCKED LOOP APPLICATIONSFREQUENCY SYNTHESISFrequency Multiplication can be achieved with the PLL intwo ways:a.) Locking to a harmonic of the input signalb.) Insertion of a counter (digital frequencydivider) in the loopHarmonic locking is the simplest and can usually beachieved by setting the veo free-running frequency to amultiple of the input frequency and allowing the PLL tolock. A limitation on this scheme, however, is that the lockrange decreases as successively higher and weaker harmonicsare used for locking. This limits the practical harmoniclocking range to multiples of approximately less than ten.For larger multiples, the second scheme is more desirable.A block diagram of the second scheme is shown in Figure8-9. Here, the loop is broken between the veo and thephase comparator and a counter is inserted. I n this case,the fundamental of the divided veo frequency is lockedto the input frequency so that the veo is actually runningat a multiple of the input frequency. The amount ofmultiplication is determined by the counter. An obviouspractical application of this multiplication property, is theuse of the PLL in wide range frequency synthesizers.is generally necessary to filter quite heavily to remove thissum frequency component. The tradeoff, of course, is areduced capture range and a more underdamped looptransient response.For the case of frequency fractionalization, both harmoniclocking and frequency countdown could be used togenerate, for instance, a frequency exactly 16/3 the input.In this case, the circuit of Figure 8-10 could be used withthe initial VCO frequency set to approximately 16/3 theexpected input frequency. The counter then divides theveo frequency by 16, and the input is locked to the 3rdharmonic of the counter output. Now the output can betaken as the veo output and it will be exactly 16/3 of theinput frequency as long as the loop is in lock.IMPLEMENTATION OF FREQUENCYSYNTHESIZER (565)+5Vn = 2n =4n =8BLOCK DIAGRAM OF FREQUENCY SYNTHESIZERUSING FREQUENCY DIVIDERn = 16IN PUT~PHASECOMPARATORfo ILOW PASS- ~ AMPLIFIERFILTER7n VCO ~Figure 8-10(Figure 8-9In frequency multiplication applications it is important totake into account that the phase comparator is actually amixer and that its output contains sum and differencefrequency components. The difference frequency componentis dc and is the error voltage which drives the veo tokeep the PLL in lock. The sum frequency components (ofwhich the fundamental is twice the frequency of the inputsignal) if not well filtered, will induce incidental FM on theveo output. This occurs because the veo is running atmany times the frequency of the input signal and the sumfrequency component which appears on the control voltageto the veo causes a periodic variation of its frequencyabout the desired multiple. For frequency multiplication itFrequency translation can be achieved by adding a mixerand a low pass filter stage to the basic PLL as shown inFigure 8-11. With this system the PLL can be used totranslate the frequency of a highly stable but fixedfrequencyreference oscillator by a small amount infrequency.In this case, the reference input fR and the veo output foare applied to the inputs of the mixer stage. The mixeroutput is made up of the sum and the differencecomponents of fR and f o . The sum component is filteredby the first low pass filter. The translation or offsetfrequency f1 is applied to the phase comparator along withthe fR - fo component of the mixer output. When thesystem is in lock, the two inputs of the phase comparatorare at identical frequency, that is,19
PHASE LOCKED LOOP APPLICATIONSFREQUENCY TRANSLATION OR "OFFSET" LOOPOFFSETINPUT f,fOOUTPUTL-------I~ fO = fR + f,Figure 8-11FREQUENCY SYNCHRONIZATIONUsing the phase locked loop system, the frequency of theless precise veo can be phase locked with a low level buthighly stable reference signal. Thus, the veo outputreproduces the reference signal frequency at the sameper-unit accuracy, but at a much higher power level. Insome applications, the synchronizing signal can be in theform of a low duty cycle burst at a specific frequency.Then, the PLL can be used to regenerate a coherent ewreference frequency blocking onto this short synchronizingpulse. A typical example of such an application isseen in the phase locked chroma-reference generators ofcolor television receivers.In digital systems, the PLL can be used for a variety ofsynchronization functions. For example, two system clockscan be phase locked to each other such that one canfunction as a back up for the other; or PLLs can be usedin synchronizing disk or tape drive mechanisms ini nformati on storage and retrieva I systems. In pu Ise-codemodulation (peM) telemetry receivers or in repeatersystems, the PLL is used for bit synchronization.Other popular applications include locking to WWVB togenerate a cheap laboratory frequency standard andsynchronizing tape speed for playback of a tape recordedat an irregular speed.SIGNAL CONDITIONINGBy proper choice of the veo free-running frequency, thePLL can be made to lock to anyone of a number ofsignals present at the input. Hence, the veo outputreproduces the frequency of the desired signal, whilegreatly attenuating the undesired frequencies of sidebandspresent at the input.If the loop bandwidth is sufficiently narrow, the signal-tonoiseratio at the veo output can be much better than thatat the input. Thus, the PLL can be used as a noise filter forregenerating weak signals buried in noise.AM DEMODULATIONAM demodulation may be achieved with PLL by thescheme shown in Figure 8-12. In this mode of operation,the PLL functions as a synchronous AM detector. The PLLlocks on the carrier of the AM signal so that the veooutput has the same frequency as that of the carrier but noamplitude modulation. The demodulated AM is thenobtained by multiplying the veo signal with the modulatedinput signal and filtering the output to remove all butthe difference frequency component. It may be recalledfrom the initial discussion that when the frequency of theinput signal is identical to the free-running frequency of theveo, the loop goes into lock with these signals 90 0 out ofphase. If the input is now shifted 90 0 so that it is in phasewith the veo signal and the two signals are mixed in asecond phase comparator, the average dc value (differencefrequency component) of the phase comparator outputwill be directly proportional to the amplitude of the inputsignal.The PLL still exhibits the same capture range phenomenadiscussed earlier so that the loop has an inherent highdegree of selectivity centered about the free-running veofrequency. Because th:' .11ethod is essentially a coherentdetection technique which involves· averaging of the twocompared signals, it offers a higher degree of noiseimm~nity than can be obtained with conventional peakdetector-typeAM demodulators.COHERENT AMPLITUDE-MODULATIONDETECTION USING A PHASE-LOCKED LOOPFigure 8-1220
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Page 4: SECTIONINTRODUCTIONPHASE LOCKED LOO
Page 7 and 8: USER'S QUICK-LOOK GUIDE TO SIGNETIC
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