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PHASE LOCKED LOOP APPLICATIONSFREQUENCY SYNTHESISFrequency Multiplication can be achieved with the PLL intwo ways:a.) Locking to a harmonic of the input signalb.) Insertion of a counter (digital frequencydivider) in the loopHarmonic locking is the simplest and can usually beachieved by setting the veo free-running frequency to amultiple of the input frequency and allowing the PLL tolock. A limitation on this scheme, however, is that the lockrange decreases as successively higher and weaker harmonicsare used for locking. This limits the practical harmoniclocking range to multiples of approximately less than ten.For larger multiples, the second scheme is more desirable.A block diagram of the second scheme is shown in Figure8-9. Here, the loop is broken between the veo and thephase comparator and a counter is inserted. I n this case,the fundamental of the divided veo frequency is lockedto the input frequency so that the veo is actually runningat a multiple of the input frequency. The amount ofmultiplication is determined by the counter. An obviouspractical application of this multiplication property, is theuse of the PLL in wide range frequency synthesizers.is generally necessary to filter quite heavily to remove thissum frequency component. The tradeoff, of course, is areduced capture range and a more underdamped looptransient response.For the case of frequency fractionalization, both harmoniclocking and frequency countdown could be used togenerate, for instance, a frequency exactly 16/3 the input.In this case, the circuit of Figure 8-10 could be used withthe initial VCO frequency set to approximately 16/3 theexpected input frequency. The counter then divides theveo frequency by 16, and the input is locked to the 3rdharmonic of the counter output. Now the output can betaken as the veo output and it will be exactly 16/3 of theinput frequency as long as the loop is in lock.IMPLEMENTATION OF FREQUENCYSYNTHESIZER (565)+5Vn = 2n =4n =8BLOCK DIAGRAM OF FREQUENCY SYNTHESIZERUSING FREQUENCY DIVIDERn = 16IN PUT~PHASECOMPARATORfo ILOW PASS- ~ AMPLIFIERFILTER7n VCO ~Figure 8-10(Figure 8-9In frequency multiplication applications it is important totake into account that the phase comparator is actually amixer and that its output contains sum and differencefrequency components. The difference frequency componentis dc and is the error voltage which drives the veo tokeep the PLL in lock. The sum frequency components (ofwhich the fundamental is twice the frequency of the inputsignal) if not well filtered, will induce incidental FM on theveo output. This occurs because the veo is running atmany times the frequency of the input signal and the sumfrequency component which appears on the control voltageto the veo causes a periodic variation of its frequencyabout the desired multiple. For frequency multiplication itFrequency translation can be achieved by adding a mixerand a low pass filter stage to the basic PLL as shown inFigure 8-11. With this system the PLL can be used totranslate the frequency of a highly stable but fixedfrequencyreference oscillator by a small amount infrequency.In this case, the reference input fR and the veo output foare applied to the inputs of the mixer stage. The mixeroutput is made up of the sum and the differencecomponents of fR and f o . The sum component is filteredby the first low pass filter. The translation or offsetfrequency f1 is applied to the phase comparator along withthe fR - fo component of the mixer output. When thesystem is in lock, the two inputs of the phase comparatorare at identical frequency, that is,19