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PHASE LOCKED LOOP APPLICATIONSINTEGRATED PHASE DETECTOR7T00- \ ~ cosL ~2n+1)Wot+Wit+O~(2n + 1) ~ lJn=OFigure 8-7The input stage formed by transistors 01 and 02 may beviewed as a differential amplifier which has a collectorresistance RC and whose differential gain at balance is theratio of RC to the emitter resistance r e of 01 and 02.0.0131eThe switching stage formed by 03 - 06 is switched on andoff by the VCO square wave. Since the collector currentswing of 02 is the negative of the collector current swing of01, the switching action has the effect of multiplying thedifferential stage output first by +1 and then by -1. Thatis, when the base of 04 is positive, RC2 receives 11 andwhen the base of 06 is positive, RC2 receives 12 = -11.Since we have called this a multiplier, let us perform themUltiplication to gain further insight into the action of thephase detector.Suppose we have an input signal which consists of twoadded components: a component at frequency Wi which isclose to the free-running frequency and a component atfrequency wk which may be at any frequency. The inputsignal isVi + Vk = Vi sin (Wit + 0i) + Vk sin (wkt + Ok)where 0i and Ok are the phase in relation to the VCOsignal. The unity square wave developed in the multiplierby the VCO signal is47T(2n + 1)sin [(2n + 1) wot]where Wo is the VCO frequency. Multiplying the twoterms, using the appropriate trigonometric relationship andinserting the differential stage gain Ad, we get00-[n=OAssuming the Vk is zero, temporarily, if Wi is close to w o 'the first term (n = 0) has a low frequency differencefrequency component. This is the beat frequency componentthat feeds around the loop and causes lock up bymodulating the VCO. As Wo is driven closer to Wi, thisdifference component becomes lower and lower in frequencyuntil Wo = Wi and lock is achieved. The first termthen becomes7Twhich is the usual phase detector formula showing the dccomponent of the phase detector during lock. Thiscomponent must equal the voltage necessary to keep theVCO at WOo It is possible for Wo to equal Wi momentarilyduring the lock up process and, yet, for the phase to beincorrect so that Wo passes through Wi without lock beingachieved. This explains why lock is usually not achievedinstantaneously, even when Wi = Wo at t = O.16