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TABLE OF CONTENTSSECTION TITLE PAGE3Introduction 5Phase Locked Loop Terminology 72 9The Phase Locked Loop Principle 11Phase Locked Loop Building Blocks 15Functional Applications 183 21General Loop Setup and Tradeoffs 23PLL Measurement Techniques 26Monolithic Phase Locked Loops 30Expanding Loop Capability 424 49Specific Applications 51

COPYRIGHT 1972SIGNETICS CORPORATIONSignetics Corporation reserves the right to make changes in the products contained inthis book in order to improve design or performance and to supply the best possibleproduct.Signetics Corporation assumes no responsibility for the use of any circuits describedherein and makes no representations that they are free from patent infringement.o25% to 50% recycled paper2

SECTIONINTRODUCTIONPHASE LOCKED LOOP TERMINOLOGY3

PHASE LOCKED LOOP APPLICATIONSINTRODUCTIONPhase Locked Loops (PLLs) are a new class of monolithiccircuits developed by Signetics, but they are based onfrequency feedback technology which dates back 40 years.A phase locked loop is basically an electronic servo loopconsisting of a phase detector, a low pass filter and avoltage controlled oscillator. Its controlled oscillator phasemakes it capable of locking or synchronizing with anincoming signal. If the phase changes, indicating theincoming frequency is changing, the phase detector outputvoltage increases or decreases just enough to keep theoscillator frequency the same as the incoming frequency,preserving the locked condition. Thus, the average voltageapplied to the controlled oscillator. is a function of thefrequency of the incoming signal. In fact, the low passfilter voltage is the demodulated output when the incomingsignal is frequency modulated (provided the controlledoscillator has a linear voltage-to-frequency transfer characteristic).The synchronous reception of radio signals usingPLL techniques was described (Ref. 1) in the early thirties.You may have heard of the "homodyne" receiver.The first widespread use of phase lock, however, was in TVreceivers to synchronize the horizontal and vertical sweeposcillators to the transmitted sync pulses. Lately, narrowbandphase locked receivers have proved to be of considerablebenefit in tracking weak satellite signals because oftheir superior noise immunity. Applications such as thesewere implemented primarily in discrete component formand involved considerable complexity even after the adventof transistors. This complexity made PLL techniquesimpractical or uneconomical in the majority of systems.The development of complete, single-chip phase lockedloops has changed this situation considerably. Now, a singlepackaged device with a few external components will offerthe user all the benefits of phase locked loop operation,including independent center frequency and bandwidthadjustment, high noise immunity, high selectivity, highfrequency operation and center frequency tuning by meansof a single external component.Signetics makes three basic classes of single-chip PLLcircuits: the general purpose PLL, the PLL with an addedmultiplier and the PLL tone decoder.The 560B, 562B and 565 are general purpose phase lockedloops containing an oscillator, phase detector and amplifier.When locked to an incoming signal, they provide twooutputs: a voltage proportional to the frequency of theincoming signal (FM output) and the square wave oscillatoroutput which, during lock, is equal to the incomingfrequency. All general purpose devices are optimized toprovide a linear frequency-to-voltage transfer characteristic.The 561 B contains a complete PLL as those above, plusthe additional multiplier or quadrature phase detectorrequired for AM demodulation. In addition to the standardFM and oscillator outputs, it also provides an outputvoltage which is proportional to the amplitude of theincoming signal (AM output). The 561 B is optimized forhighly linear FM and AM demodulation.The 567 is a special purpose phase locked loop intendedsolely for use as a tone decoder. It contains a complete PLLincluding oscillator, phase detector and amplifier as well asa quadrature phase detector or multiplier. If the signalamplitude at the locked frequency is above a minimal value,the driver amplifier turns on, driving a -load as much as200mA. It, thus, gives an output whenever an in-band toneis present. The 567 is optimized for both center frequencyand bandwidth stability.The 566 is not a phase locked loop, but a precision voltagecontrollablewaveform generator derived from the oscillatorof the 565 general purpose loop. Because of its similarity tothe 565 and because it lends itself well to use in, and inconjunction with, phase locked loops, it has been includedin this section.Table 8-1 summarizes the characteristics of Signetics phaselocked loop products.5

USER'S QUICK-LOOK GUIDE TO SIGNETICS PLLsOutputSwingUpper Maximum ±5%Frequency Lock Range FM Deviation(MHz) (% fo) Distortion (volts p.p.)NE560 30 40% .3% 1NE561 30 40% .3% 1NE562 30 40% .5% " 1NE565 .5 120% .2% .15SE565 .5 120% .2% .15NE567 .5 14% 5%* .20SE567 .5 14% 5%* .20NE566 .5 .2% 30%/V***SE566 .5 .2% 30%/V***CenterFrequencyStability(ppm/oC)±600±600±600±200±10035±6035±60±200±100FrequencyDrift with Typical SupplySupply AM Supply VoltageVoltag-e Input Output Current Range(%/volt) Resistance Available (mA) (volts).3 2K** No 9 +15 to +26.3 2K** Yes 10 +15 to +26.3 2K** No 12 +15 to +30.16 5K No 8 ± 5 to ±12.08 5K No 8 ± 5 to ±12.7 20K** Yes* 7 + 4.5 to +9.5 20K** Yes* 6 + 4.5 to +9.16 7 +10 to +26.08 7 +10 to +26(I)zQI­

PHASE LOCKED LOOP APPLICATIONSA considerable quantity of detailed specifications andpublications information for these products is included inthe Linear Spec. Handbook. Because many readers arelikely to be unfamiliar with the terminology and operatingcharacteristics of phase locked loops, a glossary of termsand a general explanation of PLL principles are includedhere with a detailed discussion of the action of theindividual loop elements.The tradeoff and setup section wi" assist the reader insome of the considerations involved in selecting andapplying the loop products to meet system requirements.A brief summary of measurement techniques has beenpresented to aid the user in achieving his performance goals.Detailed descriptions have been provided for each of theloop products. The user can supplement the suggested, connection diagrams with his own schemes.>;c ••Perhaps the best way to become familiar with the manyuses of phase locked loops is to actually study the variousapplication circuits provided. These circuits have beendrawn from many sources - textbooks, users, Signetics'applications engineers and the 1970 Signetics-EDN PhaseLocked Loop contest. Every effort has been made toprovide usable, workable circuits which may be copieddirectly or used as jumping-off points for other imaginativeappl ications.The section on interfacing wi" aid the user in drivingdifferent forms of logic from PLL outputs and the sectionon expanding loop capabilities wi" show how to achieveimproved performance in certain difficult applications.PHASE LOCKED LOOP TERMINOLOGYThe following is a brief glossary of terms encountered inPLL literature.CAPTURE RANGE (2 wC) - Although the loop wi"remain in lock throughout its lock range, it may not be ableto acquire lock at the tracking range extremes. The rangeover which the loo~. can acquire lock is termed capturerange. The capture range is sometimes called the LOCK-I NRANGE. (The latter refers to how close a signal must beto the center frequency before acquisition can occur. It isthus one-half the capture range or wC.)CURRENT CONTROLLED OSCILLATOR (CCO) - Anoscillator similar to a VCO in which the frequency isdetermined by an applied current.DAMPING FACTOR (n - The standard damping constantof a second order feedback system. In the case of the PLL,it refers to the ability of the loop to respond quickly to aninput frequency step without excessive overshoot.FREE-RUNNING FREQUENCY (fo' w o ) - Also called theCENTER FREQUENCY, this is the frequency at which theloop VCO operates when not locked to an input signal. Thesame symbols (f o ' w o ) used for the free-running frequencyare commonly used for the general oscillator frequency. Itis usually clear which is meant from the context.LOCK RANGE (2 wL) - The range of input frequenciesover which the loop will remain in lock. It is also called theTRACKING RANGE or HOLD-IN RANGE. (The latterrefers to how far the loop frequency can be deviated fromthe center frequency and is one-half the lock range or wL.)LOOP GAIN (K v ) - The product of the dc gains of all theloop elements, in units of (sec)-l.LOOP NOISE BANDWIDTH (BL) - A loop propertyrelated to damping and natural frequency which describesthe effective bandwidth of the received signal. Noise andsignal components outside this band are greatly attenuated.LOW PASS FILTER (LPF) - A low pass filter in the loopwhich permits only dc and low frequency voltages to travelaround the loop. It controls the capture range and the noiseand out-band signal rejection characteristics.NATURAL FREQUENCY (w n ) - The characteristic frequencyof the loop, determined mathematically by the finalpole positions in the complex plane. May be determinedexperimentally as the modulation frequency for which anunderdamped loop gives the maximum output and at whichphase error swing is the greatest.PHASE DETECTOR GAIN FACTOR (Kd) - The conversionfactor between the phase detector output voltage andthe phase difference between input and VCO signals involts/radian. At low input signal amplitudes, the gain is alsoa function of input level.PHASE DETECTOR (PO) - A circuit which compares theinput and VCO signals and produces an error voltage whichis dependent upon their relative phase difference. Thiserror signal corrects the VCO frequency during tracking.Also called PHASE COMPARATOR. A MULTIPLIER orMIXER is often used as a phase detector.QUADRATURE PHASE DETECTOR (QPD) - A phasedetector operated in quadrature (90 0 out of phase) withthe loop phase detector. It is used primarily for AMdemodulation and lock detection.VCO CONVERSION GAIN (Ko) - The conversion factorbetween VCO frequency and control voltage in radians/second/volt.VOLTAGE CONTROLLED OSCILLATOR (VCO) - Anoscillator whose frequency is determined by an appliedcontrol voltage.7

SECTIONTHE PHASE LOCKED LOOP PRINCIPLEPHASE LOCKED LOOP BUILDING BLOCKSFUNCTIONAL APPLICATIONS9

PHASE LOCKED LOOP APPLICATIONSTHE PHASE LOCKED LOOP PRINCIPLEThe phase locked loop is a feedback system comprised of aphase comparator, a low pass filter and an error amplifierin the forward signal path and a voltage-controlledoscillator (VCO) in the fe,edback path. The block diagramof a basic PLL system is shown in Figure 8-1. Detailedanalysis of the PLL as a feedback control system has beendiscussed in the literature (Ref. 2). Perhaps the single mostimportant point to realize when designing with the PLL isthat it is a feedback system and, hence, is characterizedmathematically by the same equations that apply to other,more c'onventional feedback systems. The parameters inthe equations are somewhat different, however, since thefeedback error signal in the phase locked system is a phaserather than a current or voltage signal, as is usually the casein conventional feedback systems.INPUTSIGNALVil.Iw,BLOCK DIAGRAM OF PHASE LOCKED LOOPfrequency wi and, thus, keep the PLL in lock. This selfcorrectingability of the system also allows the PLL totrack the frequency changes of the input signal once it islocked. The range of frequencies over which the PLL canmaintain lock with an input signal is defined as the "lockrange"of the system. The band of frequencies over whichthe PLL can acquire lock with an incoming signal is knownas the'capture range'lof the system and is never greater thanthe lock range.Another means of describing the operation of the PLL is toobserve that the phase comparator is in actuality amultiplier circuit that mixes the input signal with theVCO signal. This mix produces the sum and difference frequencieswi ± Wo shown in Figure 8-1. When the loop isin lock, the VCO duplicates the input frequency so that thedifference frequency component (wi - w o ) is zero;hence, the output of the phase comparator contains a dccomponent. The low pass filter removes the sum frequencycomponent (wi + w o ) but passes the dc component whichis then amplified and fed back to the VCO. Notice thatwhen the loop is in lock, the difference frequencycomponent is always dc, so the lock range is independentof the band edge of the low pass filter.LOCK AND CAPTURELOOP OPERATIONFigure 8-1A rigorous mathematical analysis of the system is quitecumbersome and will not be repeated here. However, froma qualitative point of view, the basic principle of PLLoperation can be briefly explained as follows: With nosignal input applied to the system, the error voltage V d isequal to zero. The VCO operates at a set frequency w o 'which is known as the free-running frequency. If an inputsignal is applied to the system, the phase comparatorcompares the phase and the frequency of the input withthe VCO frequency and generates an error voltage Ve(t)that is related to the phase and the frequency differencebetween the two signals. This error voltage is then filtered,amplified and applied to the control terminal of the VCO.In this manner, the control voltage V d(t) forces the VCOfrequency to vary in a direction that reduces the frequencydifference between fo and the input signal. If the inputfrequency wi is sufficiently close to w o ' the feedbacknature of the PLL causes the VCO to synchronize or lockwith the incoming signal. Once in lock, the VCO frequencyis identical to the input signal except for a finite phasedifference. This net phase difference () 0 is necessary togenerate the corrective error voltage V d to shift the VCOfrequency from its free-running value to the input signalConsider now the case where the loop is not yet in lock.The phase comparator again mixes the input and VCOsignals to produce sum and difference frequency components.Now, however, the difference component may falloutside the band edge of the low pass filter and be removedalong with the sum frequency component. If this is thecase, no information is transmitted around the loop and theVCO remains at its initial free-running frequency. As theinput frequency approaches that of the VCO, the frequencyof the difference component decreases and approaches theband edge of the low pass filter. Now some of thedifference component is passed, which tends to drive theVCO towards the frequency of the input signal. This, inturn, decreases the frequency of the difference componentand allows more information to be transmitted throughthe low pass filter to the VCO. This is essentially a positivefeedback mechanism which causes the VCO to snap intolock with the input signal. With this mechanism in mind,the term "capture range" can again be defined as thefrequency range centered about the VCO initial freerunningfrequency over which the loop can acquire lockwith the input signal. The capture range is a measure ofhow close the input signal must be in frequency to that ofthe VCO to acquire lock. The "capture range" can assumeany value within the lock range and depends primarily uponthe band edge of the low pass filter together with the closedloop gain of the system. It is this signal capturingphenomenon which gives the loop its frequency selectiveproperties.11

PHASE LOCKED LOOP APPLICATIONSIt is important to distinguish the "capture range" from the"lock range" which can, again, be defined as the frequencyrange usually centered about the VCO initial free-runningfrequency over which the loop can track the input signalonce lock has been achieved.When the loop is in lock, the difference frequencycomponent on the output of the phase comparator (errorvoltage) is dc and will always be passed by the low passfilter. Thus, the lock range is limited by the range of errorvoltage that can be generated and the corresponding VCOfrequency deviation produced. The lock range is essentiallya dc parameter and is not affected by the band edge of thelow pass filter.ASYNCHRONOUS ERROR BEAT FREQUENCYDURING THE CAPTURE PROCESSQUIESCENTLEVEL DC~Vd(t) ...- LOCKED DC LEVELTHE CAPTURE TRANSIENTThe capture process is highly complex and does notlend itself to simple mathematical analysis. However, aqualitative description of the capture mechanism may begiven as follows: Since frequency is the time derivative ofphase, the frequency and the phase errors in the loop canbe related asFigure 8-2awhere 6.w is the instantaneous frequency separationbetween the signal and Vc;O frequencies and fJ 0 is thephase difference between the input signal and VCO signals.If the feedback loop of the PLL was opened, say betweenthe low pass filter and the VCO control input, then for agiven condition of Wo and wi the phase comparator outputwould be a sinusoidal beat note at a fixed frequency 6.w.If wi and Wo were sufficiently close in frequency, this beatnote would appear at the filter output with negligibleattenuation. Now suppose that the feedback loop is closedby connecting the low pass filter output to the VCOcontrol terminal. The VCO frequency will be modulatedby the beat note. When this happens, 6.w itself willbecome a function of time. If during this modulationprocess, the VCO frequency moves closer to Wi (i.e.,dfJ odecreasing 6.w), then --decreases and the output of thed tphase comparator becomes a slowly varying function oftime. Similarly, if the VCO is modulated away from Wi,d6 0- increases and the error voltage becomes a rapidlyd tvarying function of time. Under this condition the beatnote waveform no longer looks sinusoidal; it looks like aseries of aperiodic cusps, depicted schematically in Figure8-2a. Because of its asymmetry, the beat note waveformcontains a finite dc component that pushes the averagevalue of the VCO toward Wi, thus decreasing 6.w. In thismanner, the beat note frequency rapidly decreases towardzero, the VCO frequency drifts toward Wi and the lock isestablished. When the system is in lock, 6.w is equal to zeroand only a steady-state dc error voltage remains.Figure 8-2bFigure 8-2b displays an oscillogram of the loop errorvoltage V d in an actual PLL system during the captureprocess. Note that as lock is approached, 6.w is reduced,the low pass filter attenuation becomes less and theamplitude of the beat note increases.The total time taken by the PLL to establish lock is calledthe pull-in time. Pull-in time depends on the initialfrequency and phase differences between the two signalsas well as on the overall loop gain and the low pass filterbandwidth. Under certain conditions, the pUll-in time maybe shorter than the period of the beat note and the loopcan lock without an oscillatory error transient.A specific case to illustrate this is shown in Figure 8-3.The 565 PLL is shown acquiring lock within the firstcycle of the input signal. The PLL was able to capture inthis short time because it was operated as a first order loop(no low pass filter) and the input tone-burst frequency waswithin its lock and capture range.12

PHASE LOCKED LOOP APPLICATIONSFAST CAPTURE EXHIBITEDBY FIRST ORDER LOOPLINEAR ANALYSIS FOR LOCK CONDITION -FREQUENCY TRACKINGWhen the PLL is in lock, the non-linear capture transientsare no longer present. Therefore, under lock condition, thePLL can often be approximated as a linear control system(see Figure 8-4) and can be analyzed using Laplacetransform techniques. I n this case, it is convenient to usethe net phase error in the loop (Os - eo) as the systemvariable. Each of the gain terms associated with th,e blockscan be defined as follows:Figure 8-3EFFECT OF THE LOW PASS FILTERIn the operation of the loop, the low pass filter serves adual function: First, by attenuating the high frequencyerror components at the output of the phase comparator,it enhances the interference-rejection characteristics;second, it provides a short-term memory for the PLL andensures a rapid recapture of the signal if the system isthrown out of lock due to a noise transient. The low passfilter bandwidth has the following effects on systemperform ance:a.)b.)c.)d.)The capture process becomes slower, and thepUll-in time increases.The capture range decreases.Interference-rejection properties of the PLLimprove since the error voltage caused by aninterfering frequency is attenuated further bythe low pass filter.The transient response of the loop (the responseof the PLL to sudden changes of the inputfrequency within the capture range) becomesunderdamped.conversion gain of phase detector (volt/rad)transfer characteristic of low pass filteramplifier voltage gainveo conversion gain (rad/volt-sec)Note that, since the veo converts a voltage to a frequencyand since phase is the integral of frequency, the veofunctions as an integrator in the feedback loop.The open loop transfer function for the PLL can be writtenasKv F(s)T(s) = --­swhere Kv is the total loop gain, i.e., Kv = KoKdA. Usinglinear feedback analysis techniques, the closed loop transfercharacteristics H(s) can be related to the open loopperformance asT(s)H(s) =--1 + T(s)and the roots of the characteristic system polynominal canbe readily determined by root-locus techniques.From these equations, it is apparent that the transientperformance and frequency response of the loop is heavilydependent upon the choice of filter and its correspondingtransfer characteristic, F (s).The last effect also produces a practical lim itation onthe low pass loop filter bandwidth and roll-off characteristicsfrom a stability standpoint. These points will beexplained further in the following analysis.LINEARIZED MODEL OF THE PLLAS A NEGATIVE FEEDBACK SYSTEMFigure 8-4The simplest case is that of the first order loop whereF(s) = 1 (no filter). The closed loop transfer function thenbecomesT(s)Kvs + KvThis transfer function gives the root locus as a function ofthe total loop gain Kv and the corresponding frequencyresponse shown in Figure 8-5a. The open loop pole at theorigin is due to the integrating action of the veo. Notethat the frequency response is actually the amplitude ofthe dtfference frequency component versus modulatingfrequency when the PLL is used to track a frequencymodulated input signal. Since there is no low pass filter inthis case, sum frequency components are also present onthe phase detector output and must be filtered outside ofthe loop if the difference frequency component (demodulatedFM) is to be measured.13

PHASE LOCKED LOOP APPLICATIONSROOT LOCUS AND FREQUENCYRESPONSE PLOTS OF FIRST ANDSECOND ORDER LOOPS-----Fh)0----0+jw-6----.-..... 6R,F~".R,C , l+jw-6 .6-, ,,-Figure 8-5aA1\\\ w, wThe stability problem can be eliminated by using a lag-leadtype of filter, as indicated in Figure 8-5c. This type of afilter has the transfer function1 + 72sF(s) =----1 + (71 + 72)swhere 72 = R2C and 71 = R1C, By proper choice of R2,this type of filter confines the root locus to the left halfplane and ensures stability. The lag-lead filter gives afrequency response dependent on the damping, which cannow be controlled by the proper adjustment of 71 and 72'In practice, this type of filter is important because it allowsthe loop to be used with a response between that of thefirst and second order loops and it provides an additionalcontrol over the loop transient response. If R2 = 0, the loopbehaves as a second order loop and if R2 = 00, the loopbehaves as a first order loop due to a pole-zero cancellation.Note, however, that as first order operation is approached,the noise bandwidth increases and interference rejectiondecreases since the high frequency error components in theloop are now attenuated to a lesser degree.-jwROOT LOCUSFREQUENCY RESPONSEFigure 8-5bSECOND ORDER PLL RESPONSEWITH SIMPLE LAG FILTERWith the addition of a single pole low pass filter F(s) of theform+jwF(s) =where 71 = R1C, the PLL becomes a second order systemwith the root locus shown in Figure 8-5b. Here, we againhave an open loop pole at the origin because of theintegrating action of the VCO and another open loop pole-1at a position equal to- where 71 is the time constant of71the low pass filter._jwOne can make the following observations from the rootlocus characteristics of Figure 8-5b.a.)b.)As the loop gain K v increases for a given choiceof 71, the imaginary part of the closed looppoles increase; thus, the natural frequency ofthe loop increases and the loop becomes moreand more underdamped.If the filter time constant is increased, the realpart of the closed loop poles becomes smallerand the loop damping is reduced.As in any practical feedback system, excess shifts ornon-dominant poles associated with the blocks within thePLL can cause the root loci to hend toward the right halfplane as shown by the dashed line in Figure 8-5b. This islikely to happen if either the loop gain or the filter timeconstant is too large and may cause the loop to break intosustained oscillations.FREQUENCY RESPONSEFigure8-5cIn terms of the basic gain expressions in the system, thelock range of the PLL W L can be shown to be numericallyequal to the dc loop gain2wL = 41TfL = 2Kv'Since the capture range wL denotes a transient condition,it is not as readily derived as the lock range. However, anapproximate expression for the capture range can bewritten as14

PHASE LOCKED LOOP APPLICATIONSwhere F(jw c ) is the low pass filter amplitude response atw = wL. Note that at all times the capture range is smallerthan the lock range. If the simple lag filter of Figure 8-5bis used, the capture range equation can be approximated asjfv2wcAFL~ 2 - = 2 -71 71Thus, the capture range decreases as the low pass filter timeconstant is decreased, whereas the lock range is unaffectedby the filter and is determined solely by the loop gain.Figure 8-6 shows the typical frequency-to-voltage transfercharacteristics of the PLL. The input is assumed to be a sinewave whose frequency is swept slowly over a broadfrequency range. The vertical scale is the correspondingloop error voltage. In Figure 8-6a, the input frequency isbeing gradually increased. The loop does not respond to thesignal until it reaches a frequency w1, corresponding to thelower edge of the capture range. Then, the loop suddenlylocks on the input and causes a negative jump of the looperror voltage. Next, V d varies with frequency with a slopeequal to the reciprocal of veo gain (1 /Ko) and goesthrough zero as wi = wOo The loop tracks the input untilthe input frequency reaches w2, corresponding to theupper edge of the lock range. The PLL then loses lock andthe error voltage drops to zero. If the input frequency isswept slowly back now, the cycle repeats itself, but it isinverted, as shown in Figure 8-6b. The loop recaptures thesignal at w3 and tracks it down to w4. The total captureand lock ranges of the system are:2wc = w3 - w1 and 2wL = w2 - w4Note that, as indicated by the transfer characteristics ofFigure 8-6, the PLL system has an inherent selectivityabout the center frequency set by the veo free-runningfrequency wo; it will respond only to the input signalfrequencies that are separated from Wo by less than Wc orw L, depending on whether the loop starts with or withoutan initial lock condition. The linearity of the frequency-tovoltageconversion characteristics for the PLL is determinedsolely by the veo conversion gain. Therefore, in most PLLapplications, the veo is required to have a highly linearvoltage-to-frequency transfer characteristic.PHASE LOCKED LOOP BUILDING BLOCKSVOLTAGE CONTROLLED OSCI LLATORSince three different forms of veo have been used in theSignetics PLL series, the veo details will not be discusseduntil the individual loops are described. However, a fewgeneral comments about veos are in order.When the PLL is locked to a signal, the veo voltage is afunction of the frequency of the input signal. Since theveo control voltage is the demodulated output during FMdemodulation, it is important that the veo voltage-tofrequencycharacteristic be linear so that the output is notdistorted. Over the linear range of the veo, the conversiongain is given by Ko (in radian/volt-sec).TYPICAL PLL FREQUENCY-TO-VOL TAGETRANSFER CHARACTERISTICS FORINPUT FREQUENCY INCREASINGAND DECREASINGVd:~ DIREC~SWEEP1-01----1I1 I-- 2WC --IaINCREASINGFREQUENCY+ : INCREASINGP.SWEEPbFREQUENCYVd 0 DIREi~CT-'ON"'OF"':''''r-4 -----*:......-~------ -Since the loop output voltage is the veo voltage, we canget the loop output voltage asThe gain Ko can be found from the data sheet by taking thechange in veo control voltage for a given percentagefrequency deviation and multiplying by the center frequency.When the veo voltage is changed, the frequencychange is virtually instantaneous.PHASE DETECTORFigure 8-6All Signetics phase locked loops use the same form of phasedetector-often called the doubly-balanced multiplier ormixer. Such a circuit is shown in Figure 8-7.15

PHASE LOCKED LOOP APPLICATIONSINTEGRATED PHASE DETECTOR7T00- \ ~ cosL ~2n+1)Wot+Wit+O~(2n + 1) ~ lJn=OFigure 8-7The input stage formed by transistors 01 and 02 may beviewed as a differential amplifier which has a collectorresistance RC and whose differential gain at balance is theratio of RC to the emitter resistance r e of 01 and 02.0.0131eThe switching stage formed by 03 - 06 is switched on andoff by the VCO square wave. Since the collector currentswing of 02 is the negative of the collector current swing of01, the switching action has the effect of multiplying thedifferential stage output first by +1 and then by -1. Thatis, when the base of 04 is positive, RC2 receives 11 andwhen the base of 06 is positive, RC2 receives 12 = -11.Since we have called this a multiplier, let us perform themUltiplication to gain further insight into the action of thephase detector.Suppose we have an input signal which consists of twoadded components: a component at frequency Wi which isclose to the free-running frequency and a component atfrequency wk which may be at any frequency. The inputsignal isVi + Vk = Vi sin (Wit + 0i) + Vk sin (wkt + Ok)where 0i and Ok are the phase in relation to the VCOsignal. The unity square wave developed in the multiplierby the VCO signal is47T(2n + 1)sin [(2n + 1) wot]where Wo is the VCO frequency. Multiplying the twoterms, using the appropriate trigonometric relationship andinserting the differential stage gain Ad, we get00-[n=OAssuming the Vk is zero, temporarily, if Wi is close to w o 'the first term (n = 0) has a low frequency differencefrequency component. This is the beat frequency componentthat feeds around the loop and causes lock up bymodulating the VCO. As Wo is driven closer to Wi, thisdifference component becomes lower and lower in frequencyuntil Wo = Wi and lock is achieved. The first termthen becomes7Twhich is the usual phase detector formula showing the dccomponent of the phase detector during lock. Thiscomponent must equal the voltage necessary to keep theVCO at WOo It is possible for Wo to equal Wi momentarilyduring the lock up process and, yet, for the phase to beincorrect so that Wo passes through Wi without lock beingachieved. This explains why lock is usually not achievedinstantaneously, even when Wi = Wo at t = O.16

PHASE LOCKED LOOP APPLICATIONSIf n =F 0 in the first term, the loop can lock when wi =(2n + 1) w o ' giving the dc phase detector component2AdVi7T(2n + 1)cos ()ishowing that the loop can lock to odd harmonics of thecenter frequency. The (2n + 1) term in the denominatorshows that the phase detector output is lower for harmoniclock, which explains why the lock range decreases ashigher and higher odd harmonics are used to achieve lock.Note also that the phase detector output during lock is(assuming Ad is constant) also a function of the inputamplitude Vi. Thus, for a given dc phase detector outputVd, an input amplitude decrease must be accompanied bya phase change. Since the loop can remain locked only for0i between 0 and 180 0 , the lower Vi becomes, the morereduced is the lock range.Going to the second term, we note that during lock thelowest possible frequency is Wo + wi = 2wi. A sumfrequency component is always present at the phasedetector output. This component is usually greatlyattenuated by the low pass filter capacitor connected tothe phase detector output. However, when rapid trackingis required (as with high-speed FM detection or FSKfrequencyshift keying), the requirement for a relativelyhigh frequency cutoff in the low pass filter may leave thiscomponent unattenuated to the extent that it interfereswith detection. At the very least, additional filtering maybe required to remove this component. Componentscaused by n -=1= 0 in the second term are both attenuated andof much higher frequency, so they may be neglected.Suppose that we have other frequencies represented byVk present. What is their effect for Vk -=1= O?The third term shows that Vk introduces another differencefrequency component. Obviously, if wk is close to wi, itcan interfere with the locking process since it may forma beat frequency of the same magnitude as the desiredlocking beat frequency. Suppose lock has been achieved,however, so that Wo = wi. In order for lock to bemaintained, the average phase detector output must beconstant. If Wo = wk is relatively low in frequency, thephase ()i must change to compensate for this beatfrequency. Broadly speaking, any signal in addition to thesignal to which the loop is locked causes a phase variation.Usually this is negligible since wk is often far removedfrom wi. However, it has been stated that the phase() i can move on Iy between 0 and 180 0 . Su ppose the phaselimit has been reached and Vk appears. Since it cannot becompensated for, it will drive the loop out of lock. Thisexplains vvhy extraneous signals can result in a decrease inthe lock : ange. If Vk is assumed to be an instantaneousnoise c:· )onent, the same effect occurs. When the fullswing of the loop is being utilized, noise will decrease thelock or tracking range. We can reduce this effect bydecreasing the cutoff frequency of the low pass filter sothat the Wo - wk is attenuated to a greater extent, whichillustrates that noise immunity and out-band frequencyrejection is improved (at the expense of capture range sinceWo - wi is likewise attenuated) when the low pass filtercapacitor is large.The third term can have a dc component when wk is anodd harmonic of the locked frequency so that (2n + 1)(w o - wi) is zero and ()k makes its appearance. This willhave an effect on 0i which will change the 0i versusfrequency wi. This is most noticeable when the waveformof the incoming signal is, for example, a square wave. The()k term will combine with the ()i term so that the phase isa linear function of input frequency. Other waveforms willgive different phase versus frequency functions. When theinput amplitude Vi is large and the loop gain is large, thephase will be close to 90 0 throughout the range of veoswing, so this effect is often unnoticed.The fourth term is of little consequence except that if wkapproaches zero, the phase detector output will have acomponent at the locked frequency Wo at the output. Forexample, a dc offset at the input differential stage willappear as a square wave of fundamental Wo at the phasedetector output. This is usually small and well attenuatedby the low pass filter. Since many out-band signals or noisecomponents may be present, many V k terms may becombining to influence locking and phase during lock.Fortunately, we need only worry about those close to thelocked frequency.The quadrature phase detector action is exactly the sameexcept that its output is proportional to the sine of thephase angle. When the phase () i is 90 0 , the quadraturephase detector output is then at its maximum, whichexplains why it makes a useful lock or amplitude detector.The output of the quadrature phase detector is given by:where Vi is the constant or modulated AM signal and()i ~ 90 0 in most cases so that sine ()i = 1 and7TThis is the demodulation principle of the autodyne receiverand the basis for the 567 tone decoder operation.17

~PHASE LOCKED LOOP APPLICATIONSFUNCTIONAL APPLICATIONSLOW PASS FILTERThe simplest type of low pass filter for the second orderloop is a single pole RC type shown in Figure 8-5b. I n allSignetics' loops, the resistor is internal and the capacitor isexternal. The inside resistor greatly improves the centerfrequency stability of the loop with temperature variations.Fortunately, the capture range and loop damping arerelated to the square root of this internal resistor value, sovariations in its absolute value have little effect on loopperformance. The nominal value of the internal resistorfor each loop is given in the circuit diagrams of thedetailed circuit descriptions in this chapter. The typicaltolerance on these integrated resistors is ±20%.FM TelemetryThis application involves demodulation of a frequencymodulated subcarrier of the main channel. A popularexample here is the use of the PLL to recover the SCA(storecast music) signal from the combined signal of manycommercial FM broadcast stations. The SCA signal is a67kHz frequency modulated subcarrier which puts it abovethe frequency spectrum of the normal stereo or monauralFM program material. By connecting the circuit of Figure8-8 to a point between the FM discrimator and thede-emphasis filter of a commercial band (home) FMreceiver and tuning the receiver to a station which broadcastsan SCA signal, one can obtain hours of commercialfree background music.As a functional building block, the phase locked loop issuitable for a wide variety of frequency related applications.These applications generally fall into one or more of thefollowing categories:a.)b.)c.)d.)e.)FM DemodulationFrequency SynthesizingFrequency SynchronizationSignal ConditioningAM DemodulationFM DEMODULATIONIf the PLL is locked to a frequency modulated (FM) signal,the VCO tracks the instantaneous frequency of the inputsignal. The filtered error voltage, which forces the VCO tomaintain lock with the input signal then becomes thedemodulated FM output. The linearity of this demodulatedsignal depends solely on the linearity of the VCO controlvoltage-to-frequencytransfer characteristic.510 pF 510pF0-lh-OEMFM4.7K4.7K10K4.7K1.8K~5KI2 83 9tOOlNE565.00110 l74.001 5 tJlK.. . 018lK.047lK+10 VOLTS+24 VOLTSBACKGRO UNOMUSIC (S CAl1-::-It should be noted that since the PLL is in lock during theFM demodulation process, the response is linear and can bereadily predicted from a root locus plot.FM demodulation applications are numerous; however,some of the more popular are:Broadcast FM DetectionHere, the PLL can be used as a complete I F strip, limiterand FM detector which may be used for detecting eitherwide or narrow band FM signals with greater linearity thancan be obtained by other means. For frequencies withinthe range of the VCO, the PLL functions as a self containedreceiver since it combines the functions of frequencyselectivity and demodulation. One increasingly popular useof the PLL is in scanning-receivers where a number ofbroadcast channels may be sequentially monitored bysimply varying the VCO free-running frequency.Figure 8-8Frequency Shift Keying (FSK)This refers to what is essentially digital frequencymodulation. FSK is a means for transmitting digitalinformation by a carrier which is shifted between twodiscrete frequencies. In this case, the two discretefrequencies correspond to a digital "1" and a digital "0,"respectively. When the PLL is locked to a FSK signal, thedemodulated output (error voltage) shifts between twodiscrete voltage levels, corresponding to the demodulatedbinary output. FSK techniques are often used in modems(modulator-demodulators), intended for transmitting dataover telephone lines.18

PHASE LOCKED LOOP APPLICATIONSFREQUENCY SYNTHESISFrequency Multiplication can be achieved with the PLL intwo ways:a.) Locking to a harmonic of the input signalb.) Insertion of a counter (digital frequencydivider) in the loopHarmonic locking is the simplest and can usually beachieved by setting the veo free-running frequency to amultiple of the input frequency and allowing the PLL tolock. A limitation on this scheme, however, is that the lockrange decreases as successively higher and weaker harmonicsare used for locking. This limits the practical harmoniclocking range to multiples of approximately less than ten.For larger multiples, the second scheme is more desirable.A block diagram of the second scheme is shown in Figure8-9. Here, the loop is broken between the veo and thephase comparator and a counter is inserted. I n this case,the fundamental of the divided veo frequency is lockedto the input frequency so that the veo is actually runningat a multiple of the input frequency. The amount ofmultiplication is determined by the counter. An obviouspractical application of this multiplication property, is theuse of the PLL in wide range frequency synthesizers.is generally necessary to filter quite heavily to remove thissum frequency component. The tradeoff, of course, is areduced capture range and a more underdamped looptransient response.For the case of frequency fractionalization, both harmoniclocking and frequency countdown could be used togenerate, for instance, a frequency exactly 16/3 the input.In this case, the circuit of Figure 8-10 could be used withthe initial VCO frequency set to approximately 16/3 theexpected input frequency. The counter then divides theveo frequency by 16, and the input is locked to the 3rdharmonic of the counter output. Now the output can betaken as the veo output and it will be exactly 16/3 of theinput frequency as long as the loop is in lock.IMPLEMENTATION OF FREQUENCYSYNTHESIZER (565)+5Vn = 2n =4n =8BLOCK DIAGRAM OF FREQUENCY SYNTHESIZERUSING FREQUENCY DIVIDERn = 16IN PUT~PHASECOMPARATORfo ILOW PASS- ~ AMPLIFIERFILTER7n VCO ~Figure 8-10(Figure 8-9In frequency multiplication applications it is important totake into account that the phase comparator is actually amixer and that its output contains sum and differencefrequency components. The difference frequency componentis dc and is the error voltage which drives the veo tokeep the PLL in lock. The sum frequency components (ofwhich the fundamental is twice the frequency of the inputsignal) if not well filtered, will induce incidental FM on theveo output. This occurs because the veo is running atmany times the frequency of the input signal and the sumfrequency component which appears on the control voltageto the veo causes a periodic variation of its frequencyabout the desired multiple. For frequency multiplication itFrequency translation can be achieved by adding a mixerand a low pass filter stage to the basic PLL as shown inFigure 8-11. With this system the PLL can be used totranslate the frequency of a highly stable but fixedfrequencyreference oscillator by a small amount infrequency.In this case, the reference input fR and the veo output foare applied to the inputs of the mixer stage. The mixeroutput is made up of the sum and the differencecomponents of fR and f o . The sum component is filteredby the first low pass filter. The translation or offsetfrequency f1 is applied to the phase comparator along withthe fR - fo component of the mixer output. When thesystem is in lock, the two inputs of the phase comparatorare at identical frequency, that is,19

PHASE LOCKED LOOP APPLICATIONSFREQUENCY TRANSLATION OR "OFFSET" LOOPOFFSETINPUT f,fOOUTPUTL-------I~ fO = fR + f,Figure 8-11FREQUENCY SYNCHRONIZATIONUsing the phase locked loop system, the frequency of theless precise veo can be phase locked with a low level buthighly stable reference signal. Thus, the veo outputreproduces the reference signal frequency at the sameper-unit accuracy, but at a much higher power level. Insome applications, the synchronizing signal can be in theform of a low duty cycle burst at a specific frequency.Then, the PLL can be used to regenerate a coherent ewreference frequency blocking onto this short synchronizingpulse. A typical example of such an application isseen in the phase locked chroma-reference generators ofcolor television receivers.In digital systems, the PLL can be used for a variety ofsynchronization functions. For example, two system clockscan be phase locked to each other such that one canfunction as a back up for the other; or PLLs can be usedin synchronizing disk or tape drive mechanisms ini nformati on storage and retrieva I systems. In pu Ise-codemodulation (peM) telemetry receivers or in repeatersystems, the PLL is used for bit synchronization.Other popular applications include locking to WWVB togenerate a cheap laboratory frequency standard andsynchronizing tape speed for playback of a tape recordedat an irregular speed.SIGNAL CONDITIONINGBy proper choice of the veo free-running frequency, thePLL can be made to lock to anyone of a number ofsignals present at the input. Hence, the veo outputreproduces the frequency of the desired signal, whilegreatly attenuating the undesired frequencies of sidebandspresent at the input.If the loop bandwidth is sufficiently narrow, the signal-tonoiseratio at the veo output can be much better than thatat the input. Thus, the PLL can be used as a noise filter forregenerating weak signals buried in noise.AM DEMODULATIONAM demodulation may be achieved with PLL by thescheme shown in Figure 8-12. In this mode of operation,the PLL functions as a synchronous AM detector. The PLLlocks on the carrier of the AM signal so that the veooutput has the same frequency as that of the carrier but noamplitude modulation. The demodulated AM is thenobtained by multiplying the veo signal with the modulatedinput signal and filtering the output to remove all butthe difference frequency component. It may be recalledfrom the initial discussion that when the frequency of theinput signal is identical to the free-running frequency of theveo, the loop goes into lock with these signals 90 0 out ofphase. If the input is now shifted 90 0 so that it is in phasewith the veo signal and the two signals are mixed in asecond phase comparator, the average dc value (differencefrequency component) of the phase comparator outputwill be directly proportional to the amplitude of the inputsignal.The PLL still exhibits the same capture range phenomenadiscussed earlier so that the loop has an inherent highdegree of selectivity centered about the free-running veofrequency. Because th:' .11ethod is essentially a coherentdetection technique which involves· averaging of the twocompared signals, it offers a higher degree of noiseimm~nity than can be obtained with conventional peakdetector-typeAM demodulators.COHERENT AMPLITUDE-MODULATIONDETECTION USING A PHASE-LOCKED LOOPFigure 8-1220

SECTIONGENERAL LOOP SETUP AND TRADEOFFSPHASE LOCKED LOOP MEASUREMENT TECHNIQUESMONOLITHIC PHASE LOCKED LOOP DESCRIPTIONSEXPANDING LOOP CAPABILITIES21

PHASE LOCKED LOOP APPLICATIONSGENERAL LOOP SETUP AND TRADEOFFSIn a given application, maximum PLL effectiveness can beachieved if the user understands the tradeoffs which can bemade. Generally speaking, the user is free to select thefrequency, tracking or lock range, capture range and inputamplitude.CENTER FREQUENCY SELECTIONSetting the center frequency is accomplished by selectingone or two external components. The center frequency isusually set in the center of the expected input frequencyrange. Since the loop's ability to capture is a function ofthe difference between the incoming and free-runningfrequencies, the band edges of the capture range are alwaysan equal distance (in Hz) from the center frequency.Typically, the lock range is also centered about the freerunningfrequency. Occasionally, the center frequency ischosen to be offset from the incoming so that detection ortracking range is limited on one side. This permits rejectionof an adjacent higher or lower frequency signal withoutpaying the penalty for narrow band operation (reducedtracking speed).All of Signetics' loops use a multiplier in which the inputsignal is multiplied by a unity square wave at the VCOfrequency. The odd harmonics present in the square wavepermit the loop to lock to input signals at these oddharmonics. Thus, the center frequency may be set to, say,1/3 or 1/5 of the input signal. The tracking range however,will be considerably reduced as the higher harmonics areutilized.The foregoing phase detector discussion would suggestthat the PLL cannot lock to subharmonics because thephase detector cannot produce a dc component if wi isless than WOoThe loop can lock to both odd harmonic and subharmonicsignals in practice because such signals often containharmonic components at f o . For example, a squarewave of fundamental fo/3 will have a substantial componentat fo to which the loop can lock. Even a puresine wave input signal can be used for harmonic locking ifthe PLL input stage is overdriven (the resultant internallimiting generates harmonic frequencies). Locking to evenharmonics or subharmonics is the least satisfactory sincethe input or VCO signal must contain second harmonicdistortion. If locking to even harmonics is desired, the dutycycle of the input and VCO signals must be shifted awayfrom the symmetrical to generate substantial even harmoniccontent.In evaluating the loop for a potential application, it is bestto actually compute the magnitude of the expected signalcomponent nearest f o . This magnitude can be used toestimate the capture and lock range.All of Signetics' loops are stabilized against centerfrequency drift due to power supply variations. Both the565 and the 567 are temperature compensated over theentire military temperature range (-55 to +125 0 C). Tobenefit from this inherent stability, however, the user mustprovide equally stable (or better) external components.For maximum cost effectiveness in some noncritical applications,the user may wish to trade some stability for lowercost external components.TRACKING OR LOCK RANGE CONTROLTwo things limit the lock or tracking range. First, anyVCO can only swing so far; if the input signal frequencygoes beyond this limit, lock will be lost. Second, thevoltage developed by the phase detector is proportional tothe product of both the phase and the amplitude of thein-band component to which the loop is locked. If thesignal amplitude decreases, the phase difference betweenthe signal and the VCO must increase in order tomaintain the same output voltage and, hence, the samefrequency deviation. It often happens with low inputamplitudes that even the full ±90 0 phase range of thephase detector cannot generate enough voltage to allowtracking wide deviations. When this occurs, the effectivelock range is reduced. We must, therefore, give up sometracking capability and accept greater phase errors if theinput signal is weak. Conversely, a strong input signal willallow us to use the entire VCO swing capability and keepthe VCO phase (referred to the input signal) very close to90 0 throughout the range. Note that tracking range doesnot depend on the low pass filter. However, if a lowpass filter is in the loop, it will have the effect oflimiting the maximum rate at which tracking can occur.Obviously, the LPF capacitor voltage cannot changeinstantly, so lock may be lost when large enough stepchanges occur. Between the constant frequency input andthe step-change frequency input is some limiting frequencyslew rate at which lock is just barely maintained. Whentracking at this rate, the phase difference is at its limit ofo or 180 0 . It can be seen that if the LPF cutoff frequencyis low, the loop will be unable to track as fast as if the LPFcutoff frequency is higher. Thus, when maximum trackingrate is needed, the LPF should have a high cutofffrequency. However, a high cutoff frequency LPF willattenuate the sum frequencies to a lesser extent so that ouroutput contains a significant and often bothersome signal23

PHASE LOCKED LOOP APPLICATIONSat twice the input frequency. (Remember that themultiplier forms both the sum and difference frequencies.During lock, the difference frequency is zero, but the sumfrequency of twice the locked frequency is still present.)This sum frequency component can then be filtered outwith an external low pass filter.demodulate an FM signal. Although the following discussiondwells largely on lock-up time, the same commentsapply to tracking speed.No simple expression is ayailable which adequatelydescribes the acquisition or lock-up time. This may beappreciated when we review the following factors whichinfluence lock-up time.CAPTURE RANGE CONTROLThere are two main reasons for making the low pass filtertime constant large. First, a large time constant provides anincreased memory effect in the loop so that it remains at ornear the operating frequency during momentary fading orloss of signal. Second, the large time constant integratesthe phase detector output so that increased immunity tonoise and out·band signals is obtained.a.)b.)c.)d.)e.)f.)g.)I nput phaseLow pass filter characteristicLoop dampingDeviation of input frequency from centerfrequencyI n-band input amplitudeOut-band signals and noiseCenter frequencyBesides the lower tracking rates attendant to large loopfilters, other penalties must be paid for the benefits gained.The capture range is reduced and the capture transientbecomes longer. Reduction of capture range occurs becausethe loop must utilize the magnitude of the differencefrequency component at the phase detector to drive theVCO towards the input frequency. If the LPF cutofffrequency is low, the difference component amplitude isreduced and the loop cannot swfng as far. Thus, the capturerange is reduced.CHOICE OF INPUT LEVELWhenever amplitude limiting of the in-band signal occurs,whether in the loop input stages or prior to the input, thetracking (lock) and capture range becomes independent ofsignal amplitude.Better noise and out-band signal immunity is achieved whenthe input levels are below the limiting threshold since theinput stage is in its linear region and the creation of crossmodulationcomponents is reduced. Higher input levels willallow somewhat faster operation due to greater phasedetector gain and will result in a lock range whichbecomes constant with amplitude as the phase detectorgain becomes constant. Also, high input levels will resultin a linear phase versus frequency characteristic.LOCK-UP TIME AND TRACKING SPEED CONTROLIn tracking applications, lock-up time is normally of littleconsequence, but occasions do arise when it is desirable tokeep lock-up time short to minimize data loss when noiseor extraneous signals drive the loop out of lock. Lock-uptime is of great importance in tone decoder type applications.Tracking speed is important if the loop is used toFortunately, it is usually sufficient to know how we canimprove the lock-up time and what we must tradeoff toget faster lock-up. Suppose we have set up a loop or tonedecoder and find that occasionally the lock-up transient istoo long. What can be done to improve the situationkeepingin mind the factors that influence lock?a.)Initial phase relationship between incomingsignal and VCO - This is the greatest singlefactor influencing the lock time. If the initialphase is wrong, it first drives the VCO frequencyaway from the input frequency so thatthe VCO frequency must walk back on thebeat notes. Figure 8-13 gives a typical distributionof lock-up times with the input pulseinitiated at random phase. The only way toovercome this variation is to send phase informationall the time so that a favorable phaserelationship is guaranteed at t = O. For example,a number of PLLs or tone decoders may beweakly locked to low amplitude harmonics ofpulse train and the transmitted tone phaserelatedto the same pulse train. Usually, however,the incoming phase cannot be controlled.b.) Low pass filter - The larger the low pass fjJtertime constant, the longer will be the lOCK-UPtime. We can reduce lock-up time by decreasingthe filter time constant, but in doing so, wesacrifice some of the noise immunity andout-band signal rejection which caused us touse a large filter in the first place. We must alsoaccept a sum frequency (twice the VCOfrequency) component at the low pass filterand greater phase jitter resulting from out-bandsignals and noise. I n the case of the tonedecoder (where control of the capture range isrequired since it specifies the device bandwidth)a lower value of low pass capacitorautomatically increases the bandwidth. We gainspeed only at the expense of added bandwidth.24

PHASE LOCKED LOOP APPLICATIONSPROBABILITY OF LOCK VERSUS INPUT CYCLES100%80%60%40%20%0%/VIIIf/v~NOTE:THE ABSCISSA WILL, IN GENERAL,BE DIFFERENT FOR EACH LOOPOPERATING CONDITION.10 15 20 25 30 35INPUT CYCLESFigure 8-13the lock-up time may be limited by the rate atwhich the low pass capacitor can charge withthe reduced phase detector output (see dabove).f.) Out-band signals and noise - Low levels ofextraneous signals and noise have little effecton the lock-up time, neither improving ordegrading it. However, large levels may overdrivethe loop input stage so that limitingoccurs, at which point the in-band signalstarts to be suppressed. The lower effectiveinput level can cause the lock-up time toincrease, as discussed in e above.g.) Center frequency - Since lock-up time can bedescribed in terms of the number of cycles tolock, fastest lock-up is achieved at higherfrequencies. Thus, whenever a system can beoperated at a higher frequency, lock willtypically take place faster. Also, in systemswhere different frequencies are being detected,the higher frequencies on the average will bedetected before the lower frequencies. However,because of the wide variation due toinitial phase, the reverse may be true for anysingle trial.c.) Loop damping - Loop damping for a simpletime constant low pass filter is:d.)~=2.~ 12 rKvDamping can be increased not only by reducingr, as discussed above, but also by reducing theloop gain Kv. By using the loop gain reductionto control bandwidth or capture and lockrange, we -achieve better damping for narrowbandwidth operation. The penalty for thisdamping is that more phase detector output isrequired for a given deviation so that phaseerrors are greater and noise immunity isreduced. Also, more input drive may berequired for a given deviation.I nput frequency deviation from free-runningfrequency - Naturally, the further an appliedinput signal is from the free-running frequencyof the loop, the longer it will take the loop toreach that frequency due to the charging timeof the low pass filter capacitor. Usually, however,the effect of this frequency deviation issmall compared to the variation .resulting fromthe initial phase uncertainty. Where loopdamping is very low, however, it may bepredominant.e.) In-band input amplitude - Since input amplitudeis one factor in the phase detector gainKd and since Kd is a factor in the loop gainKv, damping is also a function of inputamplitude. When the input amplitude is low,25

PHASE LOCKED LOOP APPLICATIONSPLL MEASUREMENT TECHNIQUESThis section deals with user measurements of PLLoperation. The techniques suggested are meant to help theuser in evaluating the performance of his PLL during theinitial setup period as well as to point out some pitfallsthat may obscure loop evaluation. Recognizing that theuser's test equipment may be limited, we have stressedthe techniques which require a minimum of standard testitems.CENTER FREQUENCYCenter frequency measurements are easily made byconnecting a frequency counter or oscilloscope to theVCO output of the loop. The loop should be connected inits final configuration with the chosen values of input,bypass and low pass filter capacitors. No input signalshould be present. As the center frequency is read out, itcan be adjusted to the desired value by the adjustmentmeans selected for the particular loop. It is important notto make the frequency measurement directly at the timingcapacitor unless the capacity added by the measurementprobe is much less than the timing capacitor value sincethe probe capacity will then cause a frequency error.When the frequency measurement is to be converted to adc voltage for production readout or automated testing,a calibrated phase locked loop can be used as a frequencymeter (see Applications Section).CAPTURE AND LOCK RANGEFigure 8-14a shows a typical measurement setup forcapture and lock range measurements. The signal inputfrom a variable frequency oscillator is swept linearlythrough the frequency range of interest and the loop FMoutput is displayed on a scope or (at low frequencies)X-Y recorder. The sweep voltage is applied to the X axis.CAPTURE AND LOCK RANGEMEASUREMENT SETUPFigure 8-14b shows the type of trace which results. Thelock range (also called hold-in or tracking range) is given bythe outer lines on the trace, which are formed as theincoming frequency sweeps away from the center frequency.The inner trace, formed as the frequency sweepstoward the center frequency, designates the capture range.Linearity of the VCO is revealed by the straightness of thetrace portion within the lock range. The slope (l1f/l1 V) isthe gain or conversion factor for the VCO.CAPTURE AND LOCK RANGE OSCILLOGRAMRgure 8-14bBy using the sweep technique, the effect on centerfrequency, capture range and lock range of the inputamplitude, supply voltage, low pass filter and temperaturecan be examined.Because of the lock-up time duration and variation, thesweep frequency must be very much lower than the centerfrequency, especially when the capture range is below 10%of center frequency. Otherwise, the apparent capture andlock range will be a function of sweep frequency. It is bestto start sweeping as slow as possible and, if desired, increasethe rate until capture range begins to show an apparentreduction-indicating that the sweep is too fast. Typicalsweep frequencies are in the range of 1/1000 to 1/100,000of the center frequency. I n the case of the 561 and 567,the quadrature detector output may be similarly displayedon the Y axis, as shown in Figure 8-15, showing theoutput level versus frequency for one value of inputamplitude.~--------------lPHASE DETECTOR OUTPUTS VS FREQUENCYFigure 8-14aFigure 8-1526

~PHASE LOCKED LOOP APPLICATIONSCapture and lock range measurements may also be madeby sweeping the generator manually through the band ofinterest. Sweeping must be done very slowly as the edgesof the capture range are approached (sweeping towardcenter frequency) or the lock-up transient delay will causean error in reading the band edge. Frequency should beread from the generator rather than the loop VCO becausethe VCO frequency gyrates wildly around the centerfrequency just before and after lock. Lock and unlock canbe readily detected by simultaneously monitoring the inputand VCO signals, the dc voltage at the low pass filter or theac beat frequency components at the low pass filter. Thelatter are greatly reduced during lock as opposed tofrequencies just outside of lock.FM AND AM DEMODULATION DISTORTIONThese measurements are quite straightforward. The loop issimply setup for FM or AM (561 or 567) detection and thetest signal is applied to the input. A spectrum analyzer ordistortion analyzer (HP 333 A) can be used to measuredistortion at the FM or AM output.For FM demodulation, the input signal amplitude must belarge enough so that lock is not lost at the frequencyextremes. The data sheets give the lock (or tracking) rangeas a function of input signal and the optional range controladjustments. Due to the inherent linearity of the VCOs, itmakes little difference whether the FM carrier is at thefree-running frequency or offset slightly as long as thetracking range limits are not exceeded.The faster the FM modulation in relation to the centerfrequency, the lower the value of the capacitor in thelow pass filter must be for satisfactory tracking. As thisvalue decreases, however, it attenuates the sum frequencycomponent of the phase detector output less. The demodulatedsignal will appear to have greater distortion unlessthis component is filtered out before the distortion ismeasured. The same comment applies to the measurementof AM distortion on the 561.When AM distortion is being measured, the carrierfrequency offset becomes more important. The. lowestabsolute value of carrier voltage at the modulation valleysmust be high enough to maintain lock at the frequencydeviation present. Otherwise, lock will periodically be lostand the distortion will be unreasonable. For example, thetypical tracking range as a function of input signal graph inthe 561 data sheet gives a total 3% tracking range at O.3mVrms input. Thus, for a carrier deviation of 1.5%, the carriermust not drop below O.3V rms in the modulation valleys.Naturally, the AM amplitude must not be too high or theAM information will be suppressed.NATURAL FREQUENCY (w n)Expressions for the natural frequency in terms of the loopgains and filter parameters are given in Table 8-2.EXPRESSIONS FOR wn AND ~ IN SECOND ORDER LOOPLOOP FILTER TYPE NATURAL FREQUENCY wn DAMPING ~R1"171 = R1C R21/2 wn (72+ --)72 = R2e71 +72 KoKd0ICotf£R1::T JKoKdWno I 0---71 2 KoDdTable 8-227

PHASE LOCKED LOOP APPLICATIONSThe natural frequency (w n ) of a loop in its final circuitconfiguration can be measured by applying a frequencymodulated signal of the desired amplitude to the loop(Table 8-2 shows that the natural frequency is a functionof Kd, in turn a function of input amplitude). As themodulation frequency (w m ) is increased, the phaserelationship between the modulation and recovered sinewave will go through 90 0 at Sm = wn and the outputamplitude will peak.UNDERDAMPED ~ ~ 0.3DAMPING (nAs shown in Table 8-2 in the discussion on low pass filter,damping is a function of Ko, Kd and the low pass filter.Since Ko and Kd are functions of center frequency andinput amplitude, respectively, damping is highly dependenton the particular operating condition of the loop. Dampingestimates for the desired operating condition can be madeby applying an input signal which is frequency modulatedwithin the lock range by a square wave. The low pass filtervoltage is then monitored on an oscilloscope which issynchronized to the modulating waveform, as shown inFigure 8-16. Figure 8-17 shows typical waveformsdisplayed. The loop damping can be estimated by comparingthe number and magnitude of the overshoots withthe graph of Figure 8-18, which gives the transient phaseerror due to a step in input frequency.Figure 8-17a [C ext > Ccrit- R ext = 0]CRITICALLY DAMPED ~ ~ 1Figure 8-17bOVERDAMPED ~ ~ 10MEASUREMENT SETUP FOR DISPLAYOF LOOP TRANSIENT RESPONSEFigure 8-17e [C < c crit' R ext > 0]HIGHLY OVERDAMPED ~ > 10Figure 8-16Figure 8-17d [C « c crit' R ext= 0)28

PHASE LOCKED LOOP APPLICATIONSTRANSIENT PHASE ERROR AS ANINDICATION OF DAMPING0.7 6W .----r---,-----r----,----,.---,--r------,wn0.6 I----F---=-=~--+---+---+---+--I-----I0.5 I--~~~+_\_-+---+---+---+--I-----I0.40.30.2NOISE EFFECTSThe effect of input noise on loop operation is very difficultto predict. Briefly, the input noise components near thecenter frequency are converted to phase noise. When thephase noise becomes so great that the ±90 0 permissiblephase variation is exceeded, the loop drops out of lock orfails to acquire lock. The best technique is to actually applythe anticipated noise amplitude and bandwidth to theinput and then perform the capture and lock rangemeasurements as well as perform operating tests with theanticipaterl input lel(:~1 J;,d modulation deviations. Byincluding a small safety factor in the loop design tocompensate for small processing variations, satisfactoryoperation can be assured.DAMPING-0.1 I--_FA+-C_TO_R--+_----1r--~+--- «==-++-_--+_~-0.2 I---+---+---+--~ __ -+~__+--I__---I-0.3 1.--_.1..-_....1...-_--1-_--'-_---'-_---' __ 1-----.1Figure 8-18Another way of estimating damping is to make use of thefrequency response plot measured fo~ the natural frequency(w n ) measurement. For low damping constants, thefrequency response measurement peak will be a strongfunction of damping. For high damping constants, the3dB-down point will give the damping. Table 8-3 givesthe approximate relationship.SIMPLIFIED MEASUREMENT EQUIPMENTThe majority of the PLL tests described can be done witha signal generator, a scope and a frequency counter. Mostlaboratories have these. A low-cost digital voltmeter willfacilitate accurate measurement of the VCO conversiongain. Where the need for a FM generator arises, it may bemet in most cases by the VCO of a Signetics PLL. (Seethe applications in this section.) Any of the loops may beset up to operate as a VCO by simply applying themodulating voltage to the low pass filter terminal(s). Theresulting generator may be checked for linearity by usingthe counter to check frequency as a function of modulatingvoltage. Since the VCOs may be modulated right down todc, the calibration may be done in steps. Moreover,Gardner *' shows how loop measurements may be made byapplying a constant frequency to the loop input and themodulating signal to the low pass filter terminal to simulatethe effect of a FM input so that a FM generator may beomitted for many measurements.ESTIMATING DAMPING FROM MODULATINGFREQUENCY (w m ) RESPONSEPEAK AMPLITUDELOW FREQUENCY~ AMPLITUDE.3 6.0dB.5 3.2dB.7 2.2dB1.0 1.3dB5.0 .5dBW-3d8wn1.82.12.54.310* see references29

PHASE LOCKED LOOP APPLICATIONSSIGNETICS MONOLITHIC PHASE LOCKEDLOOPSDETAILED DESCRIPTION OF 5608, 5618 AND 5628The 560B, 561 Band 562B phase locked loops are allderived from the same monolithic die with different metalinterconnections. Each device contains the same vea,phase detector and voltage regulator stage and, hence, thebasic loop parameters are the same for all three circuits.The 560B is the most fundamental of the three circuits,having a block diagram equivalent to that shown inFigure 8-1. The actual circuit diagram is shown inFigure 8-19.SCHEMATIC DIAGRAM OF 5608VCC@).-----+--~-+-_o @f----I----_-t-----+---+----+---o@LOW PASSFIL TER®Qll.-----+----~------r---r---+---oQV~~i0) ~~~~~~b~TED...I----'~_+_--_+_------_O @ FM/RF INPUTVCOOUTPUT4V~---o@ DE-EMPHASIS7Vr---+-----1~--+-=-='='~"=+--+---+--+---o0VCO FINETUNE CONTROL~-I---.JVII\r--o@CRs8.2K1.2KO TRACKRANGEPHASECOMPARATOR-=- GNDGNDFigure 8-1930

PHASE LOCKED LOOP APPLICATIONSThe VCO is a high frequency emitter-coupled multivibratorformed by transistors Q11-Q14. It operates from aregulated 7.7V supply formed by 6.3V supply formed byZener diode CR 1 (a reverse-biased base-emitter junction) inseries with the 14V regulated supply. The VCO frequencyis thus immune from supply voltage variations. Fourconstant current sources formed by Q20' Q21, Q23, Q24,and biased by CR6 and CR7 supply operating current forthe VCO. Voltage control of the frequency is achieved bya differential amplifier, Q22 and Q25. As the base voltageof Q22 increases with respect to the base voltage of Q25,additional current is supplied to the emitters of Q12 andQ13' increasing the charge and discharge current of thetiming capacitor Co' increasing the VCO frequency.Reducing the base voltage of Q22 with respect to Q25similarly reduces the VCO frequency. Two Zener diodesand two transistors, CR4, CR5, Q5 and Q10, respectively,provide level shifting which allows the VCO to be drivenby the outputs of the phase detector.The phase detector is a doubly-balanced multiplier formedby transistors Q6-Q9, Q17 and Q1S. Signal input is madeto the lower stage, biased at about 4Vby means of 2k.Qbase resistors. The upper stage is biased and driven directlyby the VCO output taken from the collector resistors ofQ12 and Q13· A differential output signal is availablebetween the collectors of Q 6 (and QS) and Q7 (and Q9)·An external network, together with the 6K collectorresistors, comprises the low pass filter. The phase detectoris operated from regulated 14V appearing at the emitterof Q27. A resistor in the collector of Q25 can be shuntedwith an external capacitor to form a de-emphasis filter. Thede-emphasized signal is buffered by emitter follower Q19before being brought out.The TRACK RANGE input, pin 7 on all three loops, allowsthe user to control the total current flowing through thefrequency controlling differential amplifier Q22, Q25. Thisis done by controlling the effective emitter resistance ofQ29' the current source for Q22, Q25. Current may beadded or subtracted at pin 7 to, respectively, reduce orincrease the tracking range.SCHEMATIC DIAGRAM OF 5618VCC@DEMODULATEDSKSK6K 6K .-----+-+----l--o@LOW PASSFILTER~+----+-+---+-1--~-o~CRs.-----+----+----+--+--+--o@ ~::~io ~~~~~~~~TEDl---+--I--+----O@ FM/RF INPUT~O-~---+----~t-----Q @ DE-EMPHASISL-----1--~--4--o4VCR6S.2K3K+---+---'loNv--@OFFSETCONTROL-=- ® MULTIPLIE(QUADRATUREPHASE COMPARATOR)VCOPHASECOMPARATORFigure 8-2031

PHASE LOCKED LOOP APPLICATIONSThe 561, shown in Figure 8-20, contains all of thecircuitry of the 560 and in addition, has a quadraturephase comparator. This enables it to be used as asynchronous AM detector. The quadrature phase detectorconsists of transistors 01-04 and 015, 016 which arebiased and driven in the same manner as the loop phasedetector. However, the quadrature detector input is singleended rather than differential (as the loop phase detectorinput) and an external 90 0 phase shift network is requiredto provide the proper phase relations. The demodulatedAM output is brought out at pin 1.The 562, shown in Figure 8-21, is basically the same asthe 560 except that the loop is broken between the VCOand phase comparator. This allows a counter to beinserted in the loop for frequency multiplication applications.Transistors 01-04 provide low impedance differentialVCO outputs (pins 3 and 4), and the upper stage phasedetector inputs are brought out of the package (pins 2 and15). A bias voltage is brought out through pin 1 to providea convenient bias level for the upper stage of the phasedetector.SCHEMATIC DIAGRAM OF 5628Vcc@...-----I----+--+---o@LOW PASSFILTER~+-------~+-----4---+---r--O~o 0VCOOUTPUTS03 J-4--------+------~all J--~.---4---------4-------+---+---+---0@ i::~io ~~M~~T~~~TED.1----+---1---4-------0 @ FM/RFCR5f-----Q @ DE-EMPHASIS7VB.2KVCO1.2KPHASECOMPARATORFigure 8-2132

PHASE LOCKED LOOP APPLICATIONSINTERFACINGConnection of the Signetics 560B and 561 B phase lockedloops to external input and output circuitry is readilyaccomplished; however, as with any electrical system, thereare voltage, current and impedance limitations that must beconsidered.The inputs of the phase comparators in the 560B, 561 Band562B and the AM detector in the 561 B are biased internallyfrom a +4 volt supply; therefore, the input signals must becapacitively coupled to the PLL to avoid interfering withthis bias. These coupling capacitors should be selected togive negligible phase shift at the input frequency andimpedance of the PLL. (The capacitive impedance at theoperating frequency should be as small as possible,compared to the input resistance of the PLL.)VCO OUTPUT INTERFACING+18V +18V16560B4Oo6Vp-p+605VREFJLJLOo6V5 :..ruLp-p+605V REFFigure 8-22a Figure 8-22bThe input resistance of the phase comparator is 2000nsingle-ended, and 4000n when differentially connected.The input resistance of the AM detector is 3000n. Thesignal input to the phase comparator may be applieddifferentially if there is a common mode noise problem;however, in most applications, a single-ended input will besatisfactory. When inputs are not used differentially, theunused input may be ac-coupled to ground to double thephase detector gain at low input amplitudes.+12VFigure 8-22cThe amplitude of the input signal should be adjusted togive optimum results with the PLL. Signals of less than0.2mV rms may have an unsatisfactory signal-to-noiseratio; signals exceeding 25mV rms will have reduced AMrejection (less than 30dB). The AM detector will handleinput signals up to 200mV peak-to-peak without excessivedistortion, and will handle up to 2V peak-to-peak wheredistortion is not a factor.Figure 8-22dInterfacing of the available outputs is best described byreferring to the following diagrams. Figure 8-22 showsthe PLL VCO output as a clock circuit for logic pulsesynchronization. Figures 8-22a and 8-22b show the 560Band 561 B, respectively, connected directly to the clockcircuit; however, this configuration may be limited by lowvoltage and the possibility of too large a capacitive loadswamping the oscillator. Figures 8-22c and 8-22d showthe PLL clock output for the 560B and 561B, respectively,using the 5710 Voltage Comparator as a buffer amplifier toprovide an output voltage swing suitable for driving logiccircuits. The power supply for circuits utilizing the 5710 issplit (+12 and -6V dc).In Figure 8-23a the 560B is a FM demodulator usedfor the detection of audio information on frequencymodulated carriers. Since the lower frequency limit of thistype of information is approximately 1 Hz, capacitivecoupling may be used. However, in some applications wherecarrier shifts occur at an extremely slow rate, directcoupling from the output to load is necessary. Figure8-23b shows an alternate FM detector output configurationwhich should be used if a different output is desirable.In this case, the output is removed at pins 14 and 15. Thesepins are the terminals of the low pass filter and are in theline containing the demodulated signal. The signal level(single-ended) is about one-sixth of that at pin 9 so thatadditional amplification may be required.33

PHASE LOCKED LOOP APPLICATIONSFM DETECTOR INTERFACINGDETECTOR INTERFACING (NE561B ONL V)+1av+1a1-----.--1 ~AUDIO15K OUTPUTDE-EMPHASISCAPACITORFigure 8-23aFigure 8-24a+1avOUTPUT LOW­PILLOW-PASS PASS FILTERFILTER (IF REO'Dj....----, r-----1INPUT o--j 13NE5608NE561BIII~III":' IIIIIIIIIIIIOUTPUTFigure 8-23bFigure 8-24bAdditional receiving modes are illustrated in Figure 8-24for the 561 B only. Figure 8-24a shows the 561 B outputwhen used as an AM detector; note the straight capacitivecoupling. Figure 8-24b shows the 561 B used as acontinuous wave detector. Since this version of the circuitis for the detection of ew or AM signals, external circuitrymust be incorporated for use with ew inputs. With a ew. input applied, there will be a dc shift at the output of theAM detector, pin 1. This shift is small compared to the nosignaldc level and may be difficult to detect in relation topower supply voltage changes. Therefore, a reference mustbe generated to track any power supply voltage variationsand to compensate for internal PLL thermal drift. This isbest accomplished by simulating a portion of the PLLinternal structure. The 2N3565 npn transistor is used as aconstant-current source. Its reference voltage is obtainedfrom an internal PLL bias source at pins 12 and 13, withthe current level established by the 6.8K resistor. The 6.2Kresistor and the 2.5K potentiometer simulate the PLLoutput resistance. The differential amplifier, composed oftwo 2N3638 pnp transistors, amplifies the dc output andallows it to drive a npn transistor referenced to ground.This type of circuit may also be used as a tone detector orto sense that the PLL is locked to an incoming signal.The 562 phase locked loop is especially designed forutilizing the output of the veo. In this configuration, anamplifier-buffer has been added to the veo to providedifferential square wave outputs with a 4.5V amplitude(see block diagram Figure 8-25). This facilitates theutilization of the frequency stabilized veo as a timing orclocking signal. The outputs (pins 3 and 4) are emitterfollowersand have no internal load resistors; therefore,external 3K to 12K n load resistors are required.SIGNALINPUTSBLOCK DIAGRAM OF 562BLOW-PASSFILTERFigure 8-25DE·EMPHASIS34

PHASE LOCKED LOOP APPLICATIONSIt is essential that the resistance from each pin to ground beequal in order to maintain output waveform symmetry andto minimize frequency drift. When locking the VCO outputto the phase comparator (pins 3 to 2 for single-endedconnection), capacitive coupling should be used. If a signalexceeding 2V is to be applied, a 1 K n resistor should beplaced in series with the coupling capacitor. This resistormay be part of the load resistance of 12K n, by using tworesistors (1 K and 11 K) to form the VCO load, as shown inFigure 8-26.LEVEL SHIFTING 5628 VCOOUTPUT FOR DRIVING LOGIC16+18V +5VOUTPUTTO LOGICATTENUATING INPUT TO 5628 PHASE DETECTOR121

PHASE LOCKED LOOP APPLICATIONSSIMPLI FI ED DIAGRAM OF 565 VCOr-----------.------n+vThe actual circuit is shown in Figure 8-30. Transistors01-07 and diodes 01-03 form the precision currentsource. The base of 01 is the control voltage input to theVCO. This voltage is transferred to pin 8 where it isapplied across the external resistor R 1. This develops acurrent through R 1 which enters pin 8 and becomes thecharging current for the VCO. With the exception of thenegligible 01 base current, all the current that enterspin 8, appears at the anodes of diodes 02 and D3. When08 (controlled by the Schmitt trigger) is on, 03 is reversebiased and all the current flows through 02 to theduplicating current source 05-07, R2-R3 and appears asthe capacitor discharge current at the collector of 05.When 08 is off, the duplicating current source 05-07,R2-R3 floats and the charging current passes through 03to charge C 1.Figure 8-29The Schmitt trigger (011,012) is driven from the capacitortriangle wave form by the emitter follower Og. Oiodes06-09 prevent saturation of 011 and 012, enhancingthe switching speed. The Schmitt trigger output is bufferedby emitter follower 013 and is brought out to pin 4, and isalso connected back to the current source by thedifferential amplifier (014-016).SCHEMATIC DIAGRAM OF 565RS0"CURRENT SOURCE VCO SCHMITT TRIGGER PHASE DETECTOR AMPLIFIERFigure 8-3036

PHASE LOCKED LOOP APPLICATIONSWhen operated from dual symmetrical supplies, the squarewave on pin 4 will swing between a low level of slightly(0.2V) below ground to a high level of one diode voltagedrop (O.7V) below positive supply. The triangle waveform on pin 9 is approximately centered between positiveand negative supply and has an amplitude of 2V withsupply voltages of ±5V. The amplitude of the trianglewaveform is directly proportional to the supply voltages.The phase detector is again of the doubly-balancedmodulator type. Transistors 020 and 024 form the signalinput stage, and must be biased externally. If dualsymmetrical supplies are used, it is simplest to bias 020and 024 through external resistors to ground. Theswitching stage 018, 019, 022 and 023 is driven from theSchmitt trigger via pin 5 and Dll. Diodes D12 and D13limit the phase detector output, and differential amplifier026 and 027 provides increased loop gain.The loop low pass filter is formed with an externalcapacitor (connected to pin 7) and the collector resistanceR24 (typically 3.6r2). The voltage on pin 7 becomes theerror voltage which is then connected back to the controlvoltage terminal of the VCO (base of 01). Pin 6 isconnected to a tap on the bias resistor string and providesa reference voltage which is nominally equal to the outputvoltage on pin 7. This allows differential stages to be bothbiased and driven by connecting them to pins 6 and 7.The free-running center frequency of the 565 is adjustedby means of R 1 and Cl and is given approximately by1.2f ~-­o4R1ClWhen the phase comparator is in the limiting mode(Vin ~ 200mV p-p), the lock range can be calculated fromthe expression:2wL = 2KoKdAOdThe lock range for the 565 then becomes:to each side of the center frequency, or a total range of:16f o2fL :::: -- HzVccThe capture range, over which the loop can acquire lockwith the input signal is given approximately by:where W L is the one-sided lock rangeand T is the time constant of the loop filterT = RC2with R = 3.6kr2.This can be written as:to each side of the center frequency or a total capturerange of:fc '" ~ J1T321TfOTV ccThis approximation works well for narrow capture ranges(fc = 1/3fL) but becomes too large as the limiting case isapproached (fc = f L ).where Ko is the VCO conversion gain, Kd is the phasedetector gain factor, A is the amplifier gain and Bd is themaximum phase error over which the loop can remain inlock.DETAILED DESCRIPTION OF 56650f oFor the 565: Ko =Vccradians/sec/volt(where fo is the free-running frequency of the VCO andV cc is the total supply voltage applied to the circuit.)Kd1.41TA 1.4°d1T2volts/radianradiansThe 566 is the voltage controlled oscillator portion of the565. The basic die is the same as that of the 565; modifiedmetalization is used to bring out only the VCO. The 566circuit diagram is shown in Figure 8-31. Transistor 018has been a buffered triangle waveform output. (The trianglewaveform is available at capacitor Cl also, but any currentdrawn from pin 7 will alter the duty cycle and frequency.)The square wave output is available from 019 by pin 4. Thecircuit will operate at frequencies up to 1 MHz and may beprogrammed by the voltage applied on the control terminal(pin 5), current injected into pin 6 or the value of theexternal resistor and capacitor (R 1 and C 1).37

PHASE LOCKED LOOP APPLICATIONSSCHEMATIC DIAGRAM OF 566+vl R1~(EXT) 6I5VCo-........ --C8~----~-'--------~--~------~--1---~------1-~V+Rg~------~---------+---+------~------~~--~~------~~----~--o1GNDCURRENT SOURCE VCo SCHMITT TRIGGERFigure 8-31DETAILED DESCRIPTION OF 567The 567 is a PLL designed specifically for frequencysensing or tone decoding. Like the 561, the 567 has acontrolled oscillator, a phase detector and a secondauxiliary or quadrature phase detector. In addition,however, it contains a power output stage which is drivendirectly by the quadrature phase detector output. Duringlock, the quadrature phase detector drives the outputstage on, so the device functions as a tone decoder orfrequency relay. The tone decoder center frequency andbandwidth are specified by the center frequency andcapture range of the loop portion. Since a tone decoder,by definition, responds to a stable frequency, the lock ortracking range is relatively unimportant except as it limitsthe maximum attainable capture range.The current controlled oscillator is shown in simplifiedform in Figure 8-32. It provides both a square waveoutput and a quadrature output. The control current Icsweeps the oscillator ±7% of the center frequency, which isset by external components R 1 and C1. It operates asfollows:Transistors Q1 through Q6 form a flip-flop which canswitch pin 5 between Vbe and V+ - Vbe. Thus, the R1C1network is driven from a square wave of V+ - 2V bepeak-to-peak volts. On the positive portion of the squarewave, Cl is charged through R 1 until V 1 is reached. Acomparator circuit driven from Cl at pin 6 then supplies apulse which resets the flip-flop so that pin 5 switches toVbe and Cl is discharged until V2 is reached. A secondcomparator then supplies a pulse which sets the flip-flopand Cl resumes charging.38

PHASE LOCKED LOOP APPLICATIONSSIMPLIFIED DIAGRAM OF 567 TONE DECODER CCOV+O-~--,---~------~----____ --________ --__________ ,---~4RSV+-VBE~01COMPARATOR014·018 V1R1(EXT.)VCO OUTPUTt---+------OTO PHASEFEEDBACK DETECTORCOMPARATOR024-028 V2C1(EXT.)02 r--r-+IFLlp·FLOPFigure 8-32The total swing of the capacitor voltage, as determined bythe comparator sensing voltages, isDue to the excellent matching of integrated resistors, theresistor ratio K may be considered constant. Figure 8-33shows the pin 5 and pin 6 voltages during operation. It isobvious from the proportion that t1 + t2 is independent ofthe magnitude of V+ and dependent only on the timeconstant R1C1 of the external components. Moreover, if(V 1 + V2)/2 = V+/2, then t1 = t2 and the duty cycle is50%. Note that the triangular waveform is phase shiftedfrom the square wave. A differential stage (022 and 023)amplifies the triangular wave with respect to (V1 + V2)/2to provide the quadrature output. (Due to the exponentialdistortion of the triangle wave, the quadrature output isactually phase shifted about 80 0 , but no operatingcompromises result from this slight deviation from truequadrature.)--- PINS _____ PINSFigure 8-33One source of error in this oscillator scheme is currentdrawn by the comparators from the R 1 C 1 mode. Anemitter follower, therefore, is inserted at X to minimizethis drain and 021 placed in series with 020 to drop thecomparat~r sensing voltage one Vbe to compensate for theVbe drop in the emitter follower.39

PHASE LOCKED LOOP APPLICATION.SLOOP GAIN CONSTANTS (K o , Kd)Table 8-4 gives the gain constants (K o , Kd) for theSignetics' loops. The values given are for the standardconnection with no gain reduction or tracking adjustmentcomponents connected. The dc amplifier gain A has beenincluded in either the Ko or Kd value, depending on whichside of the low pass filter terminals the gain is present. Thiscauses no hardship in calculations since the loop gain Kvbecomes simply KoKd.5608,5618,5628 565 567Korad.Single-Ended Input0.32 Wo sec-voltto veo3.0w oTotal Supply Voltagerad.rad. Differential Inputrad.O.64w = 0.67 Wo --- at ±6 volts 0.44 Woo sec-volt to veo sec-volt sec-voltKdKdVOLTS/RAD,DKdVOLTSIRAD,KVOLTS.QAD,5 .5DIFFEAENTIAL-./~TORSECONDGROUNDEi/'//, .,DIFFERENTIAL /' VIIL.-_l-L...-.5 I I--/ ./INPUT";;- VVI/.,[7 17.• r-f- INPUT OR SECOND .06 / /SINGLE-ENDED.06r-f- INPUT ACINl'UT./r-r- GROUNDED ./SlNGLE-EYEi r- V// INiT 1/ /.D'/., .D, ./ ///.06 V .L plls,1 TO'.-.006V.006./.. '.D .'D.D' / /V II INPUT.00'50100 MV-RMS ., .. , • .68'- PINS" TO ,.-ic~8~:~L~~ ,'-681-PIN7-TiiLV,'D 110 ,00 1/v1,/6I1-PIN2INPUT riiT- INPUTmV-AMS500 1000 mV-RMSlD 50'00V*The de amplifier gain A has been included in Ko or $d' depending on which side of the LPF terminals the amplifier is located.Table 8-4In order to insure that the square wave drops quickly andaccurately to Vbe, an active clamp scheme is applied tothe collector of 02. The base of 09 is held at 2 V be so thatas 02 is turned on by its base current, its collector is heldat V be. Because 02 and 03 have the same geometry andtheir base-emitter voltages are the same, the maximum02 current when clamped is essentially the same as thecollector current of 03 (as limited by R5). The flip-flopwas optimized for maximum switching speed to reducefrequency drift due to switching speed variations.Current control of the frequency is achieved by makingR21 somewhat less than R24 and restoring the propervoltage for 50% duty cycle by drawing Ic of 100,uA for theR21, 020 junction. When Ic is then varied between 0 and200,uA, the frequency changes by ±7%. Because of theslight shift in the voltage levels V 1 and V 2 with Ic, thesquare wave duty cycle changes from about 47% to about53% over the control range. To avoid drift of centerfrequency with temperature and supply voltage changeswhen Ic =1= 0, Ic is also made a function of V+ - 2Vbe·The CCO circuit is shown in the tone decoder schematicdiagram, Figure 8-34.40

PHASE LOCKED LOOP APPLICATIONSSCHEMATIC DIAGRAM OF 567R3 :'.7' r? +C3CURRENT CONTROLLEDOSCILLATORQUADRATUREPHASE DETECTORFigure 8-34A doubly-balanced multiplier formed by 032 through037 (Figure 8-34)" functions as the phase detector. Theinput signal is applied to the base of Q32. Transistors034 - Q37 are driven by a square wave taken from theCCO at the collector of Q2. Phase detector input bias isprovided by three diodes, Q38 through Q40, connected inseries, assuring good bias voltage matching from run to run.Emitter resistors R26 and R27, in addition to providingthe necessary dynamic range at the input, help stabilize thegain over the wide temperature range.The loop dc amplifier is formed by 051 and Q52. Havinga current gain of 8, it permits even a small phase detectoroutput to drive the CCO the full ±7%. Therefore, fulldetection bandwidth can be obtained for any in-band inputsignal greater than about 70mV rms. However, the mainpurpose of high loop gain in the tone decoder is to keepthe locked phase as close to 1f /2 as possible for all but thesmallest input levels since this greatly facilitates operationof the quadrature lock detector. Emitter resistors R36 andR37 help stabilize the gain over the required temperaturerange. Another function of the dc amplifier is to allow ahigher impedance level at the low pass filter terminal(pin 2) so that a smaller capacitor can be used for a givenloop cutoff frequency. Once again, emitter resistors helpstabilize the loop gain over the temperature range.The quadrature phase detector (QPO), formed by a seconddoubly-balanced mUltiplier Q42 - Q47, is driven from thequadrature output (E, F, in Figure 8-34) of the CCO. Thesignal input comes from the emitters of the inputtransistors Q32 and 033·The output stage, Q53 through 062, compares the averageOPO current in the low pass output filter R3C3 with atemperature compensated current in R39 (forming thethreshold voltage V t).Since R3 is slightly lower in value than R39, the outputstage is normally off. When the lock and the OPO currentIq occurs, pin 1 voltage drops below the threshold voltageV t and the output stage is energized.The uncommitted collector (pin 8) of the power npnoutput transi~tor can drive both 100 - 200mA loads andlogic elements, including TTL.41

PHASE LOCKED LOOP APPLICATIONSEXPANDING LOOP CAPABILITYLOW PASS FILTER CIRCUITS (560B, 561B and 562B)The low pass filters used with the 560B, 561 Band 562Bare externally adjusted to provide the desired operationalcharacteristics. To select the most appropriate type of filterand component values, a basic understanding of filteroperation is required.A FM signal to be demodulated is matched in the phasecomparator with the voltage controlled oscillator signal,which is tuned to the FM center frequency. Anyresulting phase difference between these two signals is thedemodulated FM signal, This demodulated signal isnormally at frequencies between dc and upper audiofrequencies.The choice of Iqw pass filter response gives a degree ofdesign freedom in determining the capture range orselectivity of the loop. The attenuation of the highfrequency error components at the output of the phasedetector enhances the interference rejection characteristicsof the loop. The filter also provides a short-term memoryfor the PLL that ensures rapid recapture of the signal if thesystem is thrown out of lock due to a noise transient.To ensure absolute closed loop stability at all signal levelswithin the dynamic range of the loop, the open loop PLL isrequired to have no more than 12dB per octaVe highfrequency roll-off.The capacitor in each filter circuit shown in Figure 8-35will provide 6dB per octave roll-off at the first breakpoint-the desired bandwidth frequency. The resistance Rxshown in filters (c) and (d) is used to break the response upat high frequencies to ensure 6dB per octave roll-off at theloop unity gain frequency. Rx is typically between 50 and200[2.Calculation of values for low pass filters shown can bemade using the complex second-degree transfer functionequations given, or approximated using the equation:2660C1 = -- mfd for filters (a) and (c), and the equation:f1330C1 = --mfd for filters (b) and (d) where f is the desiredffirst break frequency in Hz.At frequencies greater than 5M Hz where the loop may beprone to instability, filters (a) and (c) should be used. Foroperation at low frequencies, a simple type (b) lag filterwith no added resistance is usually sufficient.OPERATING FREQUENCY EXTENSION TO 60MHz(560B, 561 B, 562B)The frequency range of the 560B, 561 Band 562B phaselocked loops may be extended to 60MHz by the additionof two 10K n resistors from the timing capacitor terminalsto the negative power supply as shown in Figure 8-36. Theinclusion of a 5K n potentiometer between these 10K nresistors and the negative supply provides a simple methodof fine tuning.OPERATING FREQUENCY EXTENSIONFOR 560B, 561B AND 562B5608561856288 (5) 2 (6) 3Co10K10KUSE PINS (5) & (6) FOR 56285608561856288 (5) 2 (6) 3-=LOW PASS FILTER CONFIGURATIONSFigure 8-36(R = INTERNALRESISTANCE = 6Kn)INCREASED LOOP OUTPUT VOLTAGE FOR SMALLFREQUENCY DEVIATIONS (565)F(s) =HsRxC,Hs(Rx+R)C,1F(s) = HsRC,Figure 8-35_ HsRXC,F(s) - '+(2R+RX)C,C,1F(s) = H2sRC,For applications where both a narrow lock range and alarge output voltage swing are required, it is necessary toinject a constant current into pin 8 and increase the valueof R1' One scheme for this is shown in Figure 8-37. Thebasis for this scheme is the fact that the output voltagecontrols only the current through R 1 while the currentthrough Q1 remains constant. Thus, if most of the chargingcurrent is due to 01, the total current can be varied only asmall amount due to the small change in current throughR 1. Consequently, the VCO can track the input signal overa small frequency range yet the output voltage of the loop(control voltage of the VeO) will swing its maximum value.42

PHASE LOCKED LOOP APPLICATIONSNARROW BANDWIDTH FM DEMODULATOR--1~~-+---4INPUT600600Figure 8-37DEMODULATEDOUTPUTDiode 01 is a Zener diode, used to allow a larger voltagedrop across RA than would otherwise be available. 04 is adiode which should be matched to the emitter-basejunction of 01 for temperature stability. In addition, 01and 02 should have the same breakdown voltages and 03and 04 should be similar so that the voltage seen acrossR Band Re is the same as that seen across pins 10 and 1 ofthe phase locked loop. This causes the frequency of theloop to be insensitive to power supply variations. Thecenter frequencY'can be found by:HzEXPANDED LOCK RANGE (565)When the 565 is connected normally, feedback to the veofrom the phase detector is internal. That is, an amplifiermakes the pin 8 voltage track the pin 7 (phase detectoroutput) voltage. Since the capacitor e1 charge current isdetermined by the current through resistance R 1, thefrequency is a function of the voltage at pin 8. It ispossible, however, to bypass and swamp the internal loopamplifier so that the current into pin 8 is no longer afunction of the pin 8 voltage but only of the pin 7 voltage.This makes a greater charge-discharge current variationpossible, allowing a greater lock range. Figure 8-38 showssuch a circuit in which the 5741 operational amplifier is setfor a differential gain of 5, feeding current to pin 8 throughthe 33K resistor (simulating a current source). Not only isthe tracking range greatly expanded, but the output voltageas a function of frequency is five times greater than normal.In setting up such a circuit, the user should keep in mindthat for best frequency stability, the charge-dischargecurrent should be in the range of 50 to 1500JlA which alsospecifies the pin 8 input current range, showing that aratio of upper to lower lock extremes of about 30 can beachieved.EXPANDED LOCK RANGECONFIGURATION FOR 565+10Vand the total lock range is given by:8.2K22K (19 TO 1556 Hz LOCK)33K (57 TO 1910 Hz LOCK)~----~~------~~--.where: forward biased diode voltage ~ 0.7VZener diode breakdown voltagepositive supply voltagenegative supply voltagefree-running veo center frequencyWhen the output excursion at pin 7 need be only a volt orso, diodes ° 1, 02 and 03 may be replaced by shortcircuits.The value of R 1 can be selected to give a prescribed outputvoltage for a given frequency deviation.where fo is the center frequency and .6.f is the desiredfrequency deviation per volt of output.In most instances, RB and RA are chosen to be equal sothat the voltage drop across them is about 200m V. For besttemperature stability, diode ° 1 should be a base-collectorshorted transistor of the same type as 01.Figure 8-38BREAKING THE INTERNAL FEEDBACK LOOP (565)Many times it would be advantageous to be able to breakthe feedback connection between the output (pin 7) andthe control voltage terminal (01) of the veo. This can beeasily done o'nce it is seen that it is the current into pin 8which controls the veo frequency. If the external resistorR 1 is replaced with a current source, such as in Figure8-39, we have effectively broken the internal voltagefeedback connection. The current flowing into pin 8 isnow independent of .the voltage on pin 8. The outputvoltage (on pin 7) can now be amplified or filtered and usedto drive the current source by a scheme such as that shownin Figure 8-39. This scheme allows the addition of enough43

PHASE LOCKED LOOP APPLICATIONSgain for the loop to stay in lock over a 100: 1 frequencyrange, or conversely, to stay in lock with a precise phasedifference (between input and VCO signals) which is almostindependent of frequency variation. Adjustment of thevoltage to the non-inverting input of the op amp, togetherwith a large enough loop gain allows the phase difference tobe set at a constant value between 0 0 and 180 0 • Inaddition, it is now possible to do special filtering toimprove the performance in certain applications. Forinstance, in frequency multiplication applications it may bedesirable to include a notch filter tuned to the sumfrequency component to minimize incidental FM withoutexcessive reduction of capture range.INCREASED LOOP GAIN ANDLOCK RANGE FOR 565BREAKING THE INTERNAL FEEDBACK LOOP(560,561,562)The internal control voltage feedback loop can also beeasily broken on the 560, 561 and 562. The key in thiscase is to bias the range control terminal (pin 7) to +2Vwhich turns off the controlled current source. Now thephase comparator output voltage will have no effect onthe charging current which sets the VCO frequency. Nowan external feedback loop can be built with the desiredtransfer function. Figure 8-40 shows a practical applicationof this principle. The control voltage is taken fromacross the low pass filter terminals, amplified, and used toadd or subtract current into the timing capacitor nodes.MINIMIZING TONE DECODER RESPONSE TIME (567)Figure 8-39The 567 Tone Decoder is a specialized loop which can beset up to respond to a given tone (constant frequency)within its bandwidth. The center frequency is set by aresistor R 1 and capacitor C1 which determine the freerunningfrequency. The bandwidth is controlled by thelow pass filter capacitor C2' A third capacitor C3 integratesthe output of the quadrature phase detector (QPD) so thatthe dc lock-indicating component can switch the poweroutput stage on when lock is present. The 567 is optimizedfor stability and predictability of center frequency andbandwidth.+Vcc n....---------------;p---~-t____,1312INPUTSFigure 8-4044

PHASE LOCKED LOOP APPLICATIONSTwo events must occur before an output is given. First, theloop portion of the 567 must achieve lock. Second, theoutput capacitor C3 must charge sufficiently to activatethe output stage. For minimum response time, these eventsmust be as brief as possible.As previously discussed, the lock time of a loop can beminimized by reducing the response time of the low passfilter. Thus, C2 must be as small as possible. However, C2also controls the bandwidth. Therefore, the response timeis an inverse function of bandwidth as shown by Figure8-41, reprinted from the 567 data sheet. The upper curvedenotes the expected worst-case response time when thebandwidth is controlled solely by C2 and the inputamplitude is 200mV rms or greater. The response time isgiven in cycles of center frequency. For example, a 2%bandwidth at a center frequency of 1000 cycles can requireas long as 280 cycles (280ms) to lock when the initialphase relationship is at its worst. Figure 8-42 gives atypical distribution of response time versus input phase.Note that, assuming random initial input phase, only30/180 = 1/6 of the time will the lock-up time be longerthan half the worst case lock-up time. Figure 8-43 showssome actual measurements of lock-up time for a set-uphaving a worst case lock-up time of 27 cycles and a bestcaselock-up time of four input cycles.LOCK-UP TIME VARIATION DUETO RANDOM INITIAL PHASEGREATEST NUMBER OF CYCLES BEFORE OUTPUT100050040030020010050403020101.0\..'\.."\.. I\.'\ , ,,~1\ ,"""I\.'\..r- BANDWIDTH LlMIHD :>-\BANDWOOTH LIM IT'D BY C, _EXTERNAL RESISTOR2I TNrUjC ).'\.'"3 4 5 10 20 30 40 50BANDWIDTH (% of fO)Figure 8-41LOCK-UP TIME VS INITIAL PHASE100Figure 8-43The lower curve on the graph shows the worst-case lock-uptime when the loop gain is reduced as a means of reducingthe bandwidth (see data sheet, Alternate Method ofBandwidth Reduction). The value of C2 required for thisminimum response time isIt is important to note that noise immunity and rejection ofout-band tones suffer somewhat when this minimum value(C2) of C2 is used so that response time is gained at theirexpense. Except at very low input levels, input amplitudehas only a minor effect on the lock-up time-usuallynegligible in comparison to the variation caused by inputphase.J.1F.8.6.4.2oo~\\""!30'",!60 !90~--- ....INITIAL PHASE DIFFERENCE (tPj - 90)Figure 8-42 .'150-'180Lock-up transients can be displayed on a two-channel scopewith ease. Figure 8-44 shows the display which results.The top trace shows the square wave which either gates theinput generator signal off and on (or shifts the frequency inand out of the band if you have a generator which has afrequency control input only). The lower trace shows thevoltage at pin 2, the low pass filter voltage. The inputfrequency is offset slightly from the center frequency sothat the locked and unlocked voltage are different. It isapparent that, while the C2 decay during unlock is alwaysthe same, the lock transient is different each time. This isbecause the turn-on repetition rate is such that a differentinitial phase relationship occurs with each appearance ofthe in-band signal. It is tempting to adjust the repetitionrate so that a fast, constant lock-up transient is displayed.However, in doing a favorable initial phase is created that is45

PHASE LOCKED LOOP APPLICATIONSnot present in actual operation. On the contrary, it is mostrealistic to adjust the repetition rate so that the longestlock-up time is displayed, such as the fifth lock transientshows. Once this display is achieved, the effect of variousadjustments in C2 or input amplitude is seen. However,the repetition rate must be readjusted for worst-caselock-up after each such change.TONE DECODER LOCK-UP TRANSIENTIi OUTSIDE CAPTURE RANGEIi -INSIDE CAPTURE - RANGE -'\'~:~ ~',\~'RRO",OCTAG' \ 'HORT ' \ CONG(PIN 2) LOCKUP LOCK UPTIMEFigure 8-44EFFECT OF THRESHOLD VOLTAGE (V t )ADJUSTMENT ON TONE DECODERTURN-ON AND TURN-OFF DELAYLOCKIVq ----hV t ----IIII:rn .I~ ~RN-ONDELAYLOCKV q___ "'\III---...I IFigure 8-45aUNLOCK1--..lIUNLOCKIIII-------""tIIm ______....!.:--I~RN-ONDELAYFigure 8-45bTIME~RN-OFFI~ TUDELAYI-.IIhURN-OHDELAY46Once lock is achieved, the quadrature phase detectoroutput at pin 1 is integrated by C3 to extract the dccomponent. As C3 charges from its quiescent value V q(see Figure 8-45) to its final value (V q - f::,.V), it passesthrough the output stage threshdld, turning it on. Thetotal voltage change is a function of input amplitude.Since the unadjusted Vq is very close (within 50mV) to V t ,the output stage turns on very soon after lock. Only a smallfraction of the output stage time constant (r = 4700C3)expires before V t is crossed so that C3 does not greatlyinfluence the response time. However, as shown in Figure8-45a, the turn-off delay time can be quite long when C3is large. Figure 8-45b shows how desensitizing the outputstage by connecting a high-value resistor between pin 1 andpin 4 (plus supply) can equalize the turn-on and turn-offtime. If turn-off delay is important in the overall responsetime, then desensitizing can reduce the total delay.But why not make C3 very small so that these delays canbe totally neglected? The problem here is that the GPDoutput has a large twice-center-frequency component thatmust be filtered out. Also, noise, outband signals anddifference frequencies formed by close out-band frequenciesbeating with the VCO frequency appear at theGPD output. All these must be attenuated by C3 or theoutput stage will chatter on and off as the threshold isapproached. The more noisy the input signal and the largerthe near-band signals, the greater C3 must be to rejectthem. Thus, there is a complicated relationship betweenthe input spectrum and the size of C3. What must be done,then, is to make C3 more than sufficient for properoperation (no false outputs or missed signals) under actualoperating conditions and then reduce its value in smallsteps until either the required response time is obtained oroperation becomes unsatisfactory.In setting up the tone decoder for maximum speed, it isbest to proceed as follows:a.)b.)c.)After the center frequency has been set, adjustC2 to give the desired bandwidth or, if thegraph of response time in cycles (Figure 8-43)suggests that worst case lock-up time will betoo long, incorporate the loop gain reductionscheme as an alternate means of bandwidthreduction. (Page 8 of 567 data sheet.)Check lock-up time by observing the waveformat pin 2 while pulsing the input signal on andoff (or in and out of the band when a FMgenerator is used). Adjust repetition rate toreveal worst lock-up time.Starting with a large value of C3 (say 10 C2),reduce it as much as possible in steps whilemonitoring the output to be certain that nofalse outputs or missed signals occur. The fullinput spectrum should be used for this test.Ignore brief transients or chatter during turnonand turn-off as they can be eliminated withthe chatter prevention feedback techniquedescribed in the data sheet.

PHASE LOCKED LOOP APPLICATIONSd.)e.)Use the desensitizing technique, also describedin the data sheet, to balance turn-on andturn-off delay.Apply the chatter prevention technique toclean up the output.If this procedure results in a worst-case response time thatis too slow, the following suggestions may be considered:a.)b.)c.)d.)e.)Relax the bandwidth requirement.Operate the entire system at higher frequencywhen this option is available.Use two tone decoders operating at slightlydifferent frequencies and OR the outputs. Thiswill reduce the statistical occurance of theworst-case lotk-up time so that excessive lockuptime occurs. For example, if the lock-uptime is marginal 10% of the time with one unit,it will drop to 1% with two units.Control the in~band input amplitude to stabilizethe bandwidth, set up two tone decoders formaximum bandwidth and overlap the detectionbands to make the desired frequency rangeequal to the overlap. Since both tone decodersare on only when a tone appears within theoverlap range, the outputs can be ANDed toprovide the desired selectivity.If the system design permits, send the tone tobe detected continuously at a low level (say25mV rms) to keep the loop in lock at alltimes. The output stage, slightly desensitized,can then be gated on as required by increasingsignal the amplitude during the on time.Naturally, the signal phase should be maintainedas the amplitude is changed. This schemeis extremely fast, allowing repetition rates asfast as 1/3 to 1/2 the center frequency when C3is small. This is equivalent to ASK (amplitudeshift keying).47

SECTIONSPECI FIC APPLICATIONS49

PHASE LOCKED LOOP APPLICATIONSFM IF AMPLIFIER/DEMODULATOR WITH MUTING(561B)In this application, the loop portion of the 561 B operatesin the usual manner for FM demodulation. To introducemuting (squelch) the synchronous AM detector portion ofthe PLL is used to detect the presence of an input signaland to open a muting gate. Figure 8-46 shows a typicalcircuit incorporating the muting feature.The input section of the circuit is a broad-band, amplifierlimiter.The tuned LC network at the AM input, pin 4, isadjusted to provide a 90 0 phase shift at the I F frequency.This network is adjusted for maximum output at pin 1,demodulated AM output, with a carrier applied at the IFfrequency.Three transistors at the right of the diagram (01, 02 and03) and the 1 N457 diode form the muting gate. Gating isaccomplished by applying the demodulated FM outputthrough the 1 N457 diode and by biasing the diode on andoff as follows: During periods with no input applied, 01 isshut off and 02 continues. Therefore, the diode iseffectively back biased since its anode potential developedby the two 10K resistors across the power supply isapproximately +13.5V. When an input is applied to thecircuit, 01 is turned on and 02 shuts off, reducing itscollector potential below 9V. Thus, the diode is forwardbiased and the demodulated I F output is gated through tothe circuit output.Muting threshold adjustment is accomplished using the2.5K potentiometer. Transistor 03 is used as a biasgenerator for the differential pair, 0'1 and 02' In turn, thebias of 03 is obtained from internal PLL bias points atpins 12 and 13. Thus, the muting gate will track the PLLover wide temperature variations.TYPICAL FM IF AMPLIFIER/DEMODULATOR WITH MUTING+18V22K 20 J0.01 5.6K 10K lK 6.8KX2.S-12pF1612XINPUT51K51KCo137-4SpF561BAUDIOOUTPUT0.005 lK(2)0-1LOWI NPlJoTI'"I'" I 1'"10K 4.7K 6.8K":' ":'- -":'• Tl:20 TURNS BIFLAR NO. 36 WIRE ON 1/2 -WATT RESISTOR BODY (FOR 10.7 MHz)•• PART OF NE510AFigure 8-46FM DEMODU LA TOR (560B)When used as a FM demodulator, the 560B phase lockedloop requires selection of external components and/orcircuits to create the desired response .. The areas to beconsidered are:a.) Input Signal Conditioningb.) Tuning - VCO Frequencyc.) Low Pass Filter Selection/Gain Adjustmentd.) Output Swinge.) Tracking Range Adjustmentf.) De-emphasis Network SelectionFigure 8-47 illustrates schematically a typical FM demodulatorwith IF amplifier and limiter using the 560B PLL.The amplitude of the input signal has a pronounced effecton the operation. For the tracking range to be constant,the input signal level should be greater than 2mV rms. Inaddition, AM rejection diminishes at higher signal levels anddrops to less than 20dB for signals greater than 30mV. Ifeither the tracking range or AM rejection is critical, theinput signal should be conditioned to be in the 2 to 10mVrange, using either a limiter or a combination limiteramplifier.This circuit should limit at the smallest inputvoltage that is expected.51

PHASE LOCKED LOOP APPLICATIONSTYPICAL FM DEMODULATOR WITH IF AMPLIFIER AND LIMITER USING THE 560B+18V200pFr- - - ---,J T1* I 7.5KII51 1612 1514560BColK0.0113 10 DEMODULATEDFM OUTPUTlK1.5m. ~ 2~ ~0.01 Cd* TURNS NO. 36 BIFLAR WIRE WOUND ON 1/2-WATT, lOOK RESISTOR BODY** PART OF NE51 OAFigure 8-47The PLL is tuned by adjusting the VCO to the centerfrequency of the FM signal. This is accomplished byconnecting a capacitor across pins 2 and 3. The capacitorvalue is determined using the equation Co :::::: 300/f o , pFwhere f o, the free-running VCO frequency, is in MHz. Theexact value is not important as the internal resistors areonly within ±10% of nominal value and fine tuning isnormally required. Fine tuning may be accomplished byusing a trimmer capacitor in parallel with Co or by using apotentiometer connected across the power supply with therotor connected to pin 6 through a 200n current limitingresistor.The dc gain of the loop, which sets the' lock range andthreshold sensitivity, can be controlled by the placement ofa resistance between pins 14 and 15, the low pass filterterminals . .A low pass filter connected to these te'rminalscontrols the capture range or selectivity· of the loop. Inbasic terms, it may be said that the low pass filter sets thebandwidth of the demodulated information which will beobtained. For most applications, a single capacitorconnected between pins 14 and 15 will provide the requiredfiltering. The capacitance value required can be approximatedas follows:1330C~ mfdwhere f is the desired bandwidth in Hz. For example, if thedesired information bandwidth is 15kHz, the required lowpass filter capacitance will be:1330C ~ -- = .09mfd15000The output swing is a function of the frequency deviationof the incoming signal, and is approximately 0.3V p-p for.±1% deviation. For example, a standard 10.7MHz IFfrequency has a deviation of ±75kHz; therefore, the±0.75 x 100percentage deviation equals= ±0.7% and the10.7.7%output voltage will be 0.3V p-p x - = .21 V p-p, or 74mV1%rms for 100% modulation.The de-emphasis network requires an external capacitorfrom pin 10 to ground. This capacitor Cd and the 8000ninternal resistance should produce a time constant ofapproximately 75psec for standard FM broadcast demodulation.The value of the de-emphasis capacitor for thisapplication is determined by the following formula:75 x 10-68000= 0.0094 mfdFor most applicatioilS, a 0.01 mfd value would besatisfactory since the manufacturing tolerance of theresistor is on the order of 20%.52

PHASE LOCKED LOOP APPLICATIONSPHASE LOCKED AM RECEIVER (561 B)The Signetics 561 B can be used as an AM detector/receiver.AM detection is accomplished as illustrated in the blockdiagram of Figure 8-48a. The phase locked loop is lockedto the signal carrier frequency and its VCO output is usedto provide the local oscillator signal for the productdetector or synchronous demodulator. The Pll locks to itsinput signal with a constant 90 0 phase error. The amplitudeof the signal at the output of the product detector is afunction of the phase relationship of the carrier of theincoming signal and the local oscillator; it will be amaximum when the carrier and local oscillator are in phaseor 180 0 out of phase and a minimum when they are inquadrature. It is, therefore, necessary to add a 90 0 phaseshift network in the system to compensate for the normalPll phase shift. The 561 is designed for this to beincorporated between the signal input and the input to thephase comparator input, pin 12 or pin 13.+VNE561B(TOP VIEW)ICyAMINPUTFROMRF AMP ~ ......... a-----!~f--t--'PHASE LOCKED AM RECEIVERCcRyDEMODULATEDOUTPUTCB = BYPASS CAPACITORCc = COUPLING CAPACITORFigure 8-48b11.2K+VTUNING(OPTIONAl.)PHASE LOCKED AM RECEIVERAM-RF o----+----~INPUTf = c1.3 x 10- 4C = ----Y .94 x 10-61.6 x 0.55 = .94MHz then:135pFThe low pass filter for the loop, Cl, is not critical for noinformation is being derived directly from the loop errorsignal and one need only be assured of stable loopoperation. A .01 mfd capacitor was found to be adequate.Figure 8-48aConnection as an AM detector/receiver is given in Figure8-48b. The bypass and coupling capacitors should beselected for low impedance at the operating frequency.Co is selected to make the VCO oscillate at the frequencyto be received and C x is selected, in conjunction with theoutput resistance (8000n) and the load resistance, to rolloff the audio output for the desired bandwidth. The phaseshift network may be determined from the followingequations:C = y1.3 x 10- 4fcpFwhere fc is the carrier frequency of the signal to be receivedand Ry = 3000n. A receiver for standard AM receptionis easily constructed using the circuit of Figure 8-48b. Itsoperating range will be from 550kHz to 1.6MHz. All bypassand coupling capacitors are 0.1 mfd. C y is selectedusing a frequency which is the geometric mean of thelimits of the frequencies which are to be received.Tuning may be accomplished in several ways. The simplestmethod uses a variable capacitor as Co. It should betrimmed so that when set for minimum capacitance, theVCO frequency is approximately 1.6MHz. The capacitanceused may be obtained from the following formula: Co ~300pF where fo is in MHz.foApplication of this formula shows that the minimumcapacitance should be about 180pF and the maximumcapacitance should be 550pF. A second tuning methodutilizes the fine tuning input, pin 6. When current isinserted or removed from this pin, the VCO frequency willchange, thereby tuning the receiver. Select Co' when thecurrent at pin 6 is zero, to make the VCO operate at themean frequency used in the phase shift network calculation(940kHz). The complete standard AM broadcast band maynow be tuned with one potentiometer. The resistor inseries with the arm of the potentiometer is selected to givethe desired tuning range and will be about 1200n when an18V power supply is used.For operation, this receiver requires an antenna and a goodgrounding system. Operation may be improved by includinga broadband untuned RF amplifier, but care should be usedto ensure that the phase locked loop is not overdriven, e.g.input signals should be kept less than 0.5V rms.53

PHASE LOCKED LOOP APPLICATIONSIF STAGE WITH AGC AND AM/FM DETECTION (5618)The circuit shown in Figure 8-49 is basically an I F strip at10.7MHz employing a buffer amplifier, two stages of gain,two ganged stages of AGe and an AGe summing amplifier.A single 561 B PLL serves as both the AM and FM detector.Input sensitivity to insure lockup for either AM or FMdemodulation is approximately 101lV. The input level tothe 561 B is held level at 305mV p-p during input amplitudeexcursion from 10llV to 120mV p-p. Potentiometer RAGeis adjusted at no input for a quiescent dc voltage (pin 6of ampl ifier 5741) of -90m V. Th is presets the 5596multipliers at a maximum gain condition. The gain isslowly reduced as the R F input level rises and full AGeaction begins.The bandwidth of linear demodulation of AM is 1 Hz to4.5kHz and of FM is 1 Hz to 36kHz.I F gain adjustment can be provided with the installation ofa potentiometer between pins 4 and 9 of either (or both)of the 5733, a zero ohm setting insuring maximum gain.The addition of a conventional converter front-end andaudio driver stages completes the circuitry for a receiver.IF GAIN STAGE WITH AGC AND AM/FM DETECTION+6V+6V+6V0.1~~~~HZ IF o-..-il-..--£FRONTEND75 13K10.7MHzSIGNAL510IN9141ST STAGEAGe VOLTAGE-6V-6VFINETUNE100MUDIOOUTPUTNOTE, SET AGC ADJUSTCONTROL FOR 0.09 VDC0.2 AT PIN 6 OF 5741 WHENINPUT SIGNAL IS1ST STAGEAGCVOLTAGE100I INOAGeADJUSTFigure 8-4954

PHASE LOCKED LOOP APPLICATIONSTRANSLATION LOOP FOR PRECISE FM (5618,5628)A translation loop mixes the output of two oscillators andproduces a signal whose frequency is equal to the sum ordifference of the two. In the most useful application of thiscircuit, one oscillator is a precise crystal-controlledoscillator and the second is a low frequency voltagecontrolledoscillator so that the loop output is a FM signalwhose center frequency is slightly offset from the crystaloscillator frequency. Since the offset oscillator suppliesonly a small percentage of the final output frequency, itneed not be as precise as the crystal oscillator.Such a loop is shown in Figure 8-50a. The VCO is drivenuntil the filtered low frequency component of the P02output is equal to the offset frequency f m . When thisoccurs, lockup is achieved and the VCO output is eitherfR + fm or fR - f m. By adjusting the VCO free-runningslightly above f m , the latter case can be eliminated. If fmis frequency modulated, then the output will also befrequency modulated since it has the same absolutedeviation.TRANSLATION LOOP FOR PRECISION TV INTERMEDIATE-FREQUENCY FM GENERATORVCOFigure 8-50aFigure 8-50b shows a translation loop made from a 561Band 562B. It is designed to produce a 4.5MHz signal with adeviation of ±25kHz. The 561 B serves as the VCO andPO 1; the 562B serves as the crystal oscillator and PD2. A4.400MHz crystal controls the reference frequency fRoThe offset frequency fm is 100kHz frequency modulated±25kHz at a modulation frequency of 400Hz. Theaccuracy of the output frequency is that of the referenceoscillator plus that of the offset oscillator; since fm is asmall percentage (2%) of fR, its stability can be considerablyless than that of the crystal oscillator. In this case, fmcan be provided by a 566 VCO modulated, if desired, by asecond 566. (The triangle wave 566 output results in aconstant df/dt.)TRANSLATION LOOP FOR PRECISION TV INTERMEDIATE - FREQUENCY FM GENERATOR+18fm = 100KHz ± lIf(150MV-RMS)+18fR4.400 MHz cCRYSTAL-=5pF680fm11 5628.05330 14-=.05P LPFNO.243pF-=SET VCO1-15pFfR + fm =4.5MHz ± 6fFigure 8-50b55

PHASE LOCKED LOOP APPLICATIONSSpecial layout precautions are required to be sure that nohigh frequency coupling occurs via grounds or powersupply lines. The circuit is adjusted by trimming the 562VCO trimmer capacitor until the beat note present at testpoint 1 has the same frequency as f m throughout thedeviation range (f m can be deviated by hand or very slowly,say, at a 1 Hz rate, to observe that the beat note does notbreak up during sweep. If the beat note is lost at eitherextreme, adjust the VCO trimmer. If the full deviationcannot be obtained, decrease the 562 low pass filtercapacitor sl ightly. Connect a cou nter to the output to besure the loop is locked to fR + fm and not fR - fm (unlessthe latter is desired).Naturally, the component values given may be altered forother applications. Note that as fm is made a smaller andsmaller percentage of the total output frequency, itbecomes difficult to prevent locking in the fR - fm modesince the 562 lock range will likely include both fR - fmand fR + f m . However, if fm is made too large a portion ofthe output frequency, then overall stability suffers unlessf m is also qu ite precise.PHASE LOCKED FSK DEMODULATORS (5608,565)FSK refers to data transmission by means of a carrierwhich is shifted between two preset frequencies. Thisfrequency shift is usually accomplished by driving a VCOwith the binary data signal so that the two resultingfrequencies correspond to the "0" and "1" states(commonly called space and mark) of the binary datasignal.The 560B phase locked loop can be used as a recelvmgconverter to demodulate FSK audio tones and to provide ashifting dc voltage to initiate mark or space code elements.The PLL can replace the bulky audio filters andundependable relay circuits previously used for thisapplication. Connection of the 560B PLL as a FSKdemodulator is illustrated in Figure 8-51.The system functions by locking-on and tracking theoutput frequency of the receiver. The demodulatorfrequency shift appears at pin 9 as a direct-current voltageof about 60mV amplitude and must be amplified andsignal-conditioned to interface with the printer. The inputvoltage at pin 12 should be from 30mV to 2V peak-to-peak,square or sine wave. Pin 10, the de-emphasis terminal, isused for bandshaping. The capacitor connected betweenthis terminal and ground bypasses unwanted highfrequency noise to ground. Pin 9 is the output (approximately60mV dc) which is amplified, conditioned and fedto a voltage comparator amplifier (N5710) to provide theproper voltages for interfacing with the printer. Thisspecific circuit was designed to match the Bell 103C and103D Data Phones. When modifying this circuit toaccommodate other systems, maintain the resistance toground from pin 9 at approximately 15Q. Pins 3 and 2 arethe connections for the external capacitor that determinethe free-running frequency of the VCO. The 0.33MF· valueindicated provides a VCO frequency, f o ' of approximately1060Hz. The value of the timing capacitor can beCo = 300pFcalculated by use of the following equation:where fo is in Hertz.The output has a swing of 2V peak-to-peak, over a 0 to 600baud input FSK rate, with less than 10% jitter at thecomparator output. The circuit is operative over atemperature range of 0° to 75 0 C with a total drift ofapproximately 1 OOmV over the temperature range.A simple scheme using the 565 to receive FSK signals of1070Hz and 1270Hz is shown in Figure 8-52. As the signalappears at the input, the loop locks to the input frequencyand tracks it between the two frequencies with acorresponding dc shift at the output.FSK DECODER USING THE 565FSK DEMODULATOR USING 560810K10KL......;.-+---------+----o-5VFigure 8-52OUTPUTr----"."IIr-+--+---+--......... --o-6VFigure 8-51The loop filter capacitor C2 is chosen to set the properovershoot on the output and a three-stage RC ladder filteris used to remove the sum frequency component. Theband edge of the ladder filter is chosen to be approximatelyhalf-way between the maximum keying rate (30056

PHASE LOCKED LOOP APPLICATIONSbaud or bits per second, or 150Hz) and twice the inputfrequency (about 2200Hz). The free-running frequencyshould be adjusted (with R 1) so that the dc voltage level atthe output is the same as that at pin 6 of the loop. Theoutput signal can now be made logic compatible byconnecting a voltage comparator between the ,output andpin 6.The input connection is typical for cases where a dc voltageis present at the source and, therefore, a direct connectionis not desirable. Both input terminals are returned toground with identical resistors (in this case, the values arechosen to achieve a 600n input impedance.)FSK DECODER WITH EXPANDED565 OUTPUT VOLTAGE RANGEV,:z+14VFor best operation, the free-running veo frequency shouldbe adjusted so that the output voltage (corresponding tothe input frequencies of 1070Hz and 1270Hz swingsequally to both sides of the reference voltage at pin 6. Thiscan be easily done by adjusting the center frequency of theveo so that the output signal of the 5710 comparator hasa 50% duty cycle. It is usually necessary to decouple pin 6with a large capacitor connected to the positive supply inorder to obtai n a stable reference voltage for the 5710comparator.Figure 8-54 shows the output of the 5710 comparator andthe output of the 565 phase locked loop after the filter atrates of 100,200 and 300 baud, respectively.100 BAUD FSK DECODINGINPUTo---}r-.--f---IOUTPUTFigure 8-53A more sophisticated approach primarily useful for narrowfrequency deviations is shown in Figure 8-53. Here, aconstant current is injected into pin 8 by means oftransistor 01. This has the effect of decreasing the lockrange and increasing the output voltage sensitivity to theinput frequency shift. The basis for this scheme is the factthat the output voltage (control voltage for VeO) controlsonly the current through R 1, while the current through 01remains constant. Thus, if most of the capacitor chargingcurrent is due to 01, the current variation due to R 1 willbe a small percentage of the total charging current and,consequently, the total frequency deviation of the veowill be limited to a small percentage of the centerfrequency. A 0.25mfd loop filter capacitor gives approximately30% overshoot on the output pulse, as seen in theaccompanying photographs.The output is then filtered with a two-stage Re ladderfilter with a band edge chosen to be approximately 800Hz(approximately half-way between the maximum keyingrate of 150Hz and twice the carrier frequency). Thenumber of stages on the filter can be more or lessdepending on the degree of uncertainty allowable in thecomparator output pulse. Two small capacitors (typically0.001 mfd) are connected between pins 8 and 7 of the 565and across the input of the comparator to avoid possibleoscillation problems.Figure 8-54a200 BAUD FSK DECODINGFigure 8-54b300 BAUD FSK DECODIN.GF~gure 8-54c57

PHASE LOCKED LOOP APPLICATIONSANALOG LIGHT-COUPLED ISOLATORS (565,567)The analog isolator shown in Figure 8-55a is basically aFM transmission system with light as the transmissionmedium. Because of the high degree of electrical isolationachieved, low-level signals may be transmitted withoutinterference by great potential difference between thesending and receiving circuits. The transmitter is a 565used as a veo with the input applied to the veo terminal7. Since the light emitting diode is driven from the 565veo output, the LED flashes at a rate proportional to theinput voltage. The receiver is a photo transistor whichdrives an amplifier having sufficient gain to apply a 200mVpeak-to-peak signal to the input of the receiving 565,which then acts as a FM detector with the output appearingat pin 7. Since the output has a twice carrier frequencyripple, it is best to keep the carrier frequency as high aspossible (say, 100 times the highest modulation frequency).Because of the excellent temperature stability of the 565,drift is minimal even when dc levels are being transmitted.If operation to dc is not required, the output of the receivercan be capacitively coupled to the next stage. Also, a 566can be used as the transmitter.LIGHT-COUPLED ANALOG ISOLATORS+V +V +v +V +V~ 10INPUT7 565 4 t--I~+-'£OUTPUTDC LEVELADJUST'::"'-V -V -v -V~OUTPUTIFILTER CAP.Figure 8-55aFigure 8-55b shows that the 567 may be used in the samemanner when operation from 5V supplies is required. Here,the output stage of the 567 is used to drive the LEDdirectly. When the free-running frequency of the receiving567 is the same as that of the transm itting 567, thenon-linearity of the two controlled oscillator transferfunctions cancel so that highly linear information transferresults.LIGHT-COUPLED ANALOG ISOLATORS+5 +5+5OUTPUTDC LEVELADJUSTFigure 8-55b58

PHASE LOCKED LOOP APPLICATIONSFigure 8-56 is an oscillogram of the input and output ofthe Figure 8-55a circuit. The output can easily be filteredto remove the sum frequency component.PHASE MODULATION USING THE PLLWAVEFORMS OF LIGHT-COUPLEDANALOG ISOLATOR (CIRCUIT A)~~~¢j 5 6 2~:- PHASEIT CONTROL OR-::=.1 MODULATION';'" VOLTAGEFigure 8-57bPHASE MODULATORSIf a phase locked loop is locked onto a signal at the centerfrequency, the phase of the VCO will be 90 0 with respectto the input signal. If a current is injected into the VCOterminal (the low pass filter output), the phase will shiftsufficiently to develop an opposing average current out ofthe phase detector so that the VCO voltage is constant andlock is maintained. When the input signal amplitude is lowenough so that the loop frequency swing is limited by thephase detector output rather than the VCO swing, thephase can be modulated over the full range of 0 to 180 0 .If the input signal is a square wave, the phase will be alinear function of the injected current.A block diagram of the phase modulator is given in Figure8-57a. The conversion factor K is a function of which loopis used, as well as the input square wave amplitude. Figure8-57b shows an implementation of this circuit using the567.PHASE MODULATION USING THE PLL¢j+ KII------------------~IIveo IOUTPUT IIIIII L __________________ J IFigure 8-57aPHASEMOOULATIONINPUTDUAL TONE DECODERS (567)Two integrated tone decoders can be connected (as shownin Figure 8-58a) to permit decoding of simultaneous orsequential tones. Both units must be on before an output isgiven. R,C1 and R,C, are chosen, respectively, for tones1 and 2. If sequential tones (1 followed by 2) are to bedecoded, then C3 is made very large to delay turn off ofunit 1 until unit 2 has turned on and the NOR gate isactivated. Note that the wrong sequence (2 followed by 1)will not provide an output since unit 2 will turn off beforeunit 1 comes on. Figure 8-58b shows a circuit variationwhich eliminates the NOR gate. The output is taken fromunit 2, but the unit 2 output stage is biased off by R2 andCR 1 until activated by tone 1. A further variation is givenin Figure 8-58c. Here, unit 2 is turned on by the unit 1~utput when tone 1 appears, reducing the standby powerto half. Thus, when unit 2 is on, tone 1 is or was present.If tone 2 is now present, unit 2 comes on also and anoutput is given. Since a transient output pulse may appearduring unit 1 turn-on, even if tone 2 is not present, theload must be slow in response to avoid a false output dueto tone 1 alone.HIGH SPEED, NARROW BAND TONE DECODER (567)The circuit of Figure 8-58a may be used to obtain a fast,narrow band tone decoder. The detection bandwidth isachieved by overlapping the detection bands of the twotone decoders. Thus, only a tone within the overlap portionwill result in an output. The input amplitude should begreater than 70mV rms at all times to prevent detectionband shrinkage and C2 should be between 130lf o and1300/f o mfd wher~ fo is the nominal detection frequency.The small value of C2 allows operation at the maximumspeed so that worst-case output delay is only about 14cycles.59

PHASE LOCKED LOOP APPLICATIONSDETECTION OF TWO SIMULTANEOUSOR SEQUENTIAL TONESTOUCH-TONE® DECODER (567)Touch-Tone® decoding is of great interest since all sorts ofremote control applications are possible if you make useof the encoder (the push-button dial) that will ultimatelybe part of every phone. A low cost decoder can be made asshown in Figure 8-59. Seven 567 tone decoders, theirINPUT 0---}OUTPUTLOW-COST TOUCH TONE® DECODER~1 ~2~3Figure 8-58a+V +VINPUTo---}J1 ~2~3Figure 8-58b+V +VINPUT 0---1COMPONENT VALUES (TYPICAL)R, e.8to15kohmR2 4.7kohmR3 2.0kohmO.1mfdC,C2 1.0mfd 6VCa 2.2mfd evC4 250 INFigure 8-58cFigure 8-5960

PHASE LOCKED LOOP APPLICATIONSinputs connected in common to a phone line or acousticalcoupler, drive three integrated NOR gate packages. Eachtone decoder is tu ned, by means of R 1 and C1, to one ofthe seven tones. The R2 resistor reduces the bandwidth toabout 8% at 100m V and 5% at 50m V rms. Capacitor C4decouples the seven units. If you are willing to settle for asomewhat slower response at low input voltages (50 to100m V rms), the bandwidth can be controlled in thenormal manner by selecting C2, thereby eliminating theseven R2 resistors and C4. In this case, Ci would be 4.7mfdfor the three lower frequencies and 2.2mfd for the fourhigher frequencies.The only unusual feature of this circuit is the means ofbandwidth reduction using the R2 resistors. As shown inthe 567 data sheet under Alternate Method of BandwidthReduction, an external resistor RA can be used to reducethe loop gain and, therefore, the bandwidth. Resistor R2serves the same function as R A except that instead of goingto a voltage divider for dc bias it goes to a common pointwith the six other R2 resistors. In effect, the five 567swhich are not being activated during the decoding processserve as bias voltage sources for the R2 resistors of the two567s which are being activated. Capacitor C4 (optional)decouples the ac currents at the common point.LOW COST FREQUENCY INDICATOR (567)Figure 8-60 shows how two tone decoders set up withoverlapping detection bands can be used for a go/no-gofrequency meter. Unit 1 is set 6% above the desired sensingfrequency and unit 2 is set 6% below the desired frequency.Now, if the incoming frequency is within 13% of thedesired frequency, either unit 1 or unit 2 will give anoutput. If both units are on, it means that the incomingfrequency is within 1% of the desired frequency. Threelight bulbs and a transistor allow low cost read-out.CRYSTAL-STABI LlZED PHASE LOCKED LOOP (560B)Figure 8-61a shows the 560B connected as a trackingfi Iter for signals near 10M H z. The crystal keeps the freerunningfrequency at the desired value. Figure 8-61 b givesthe lock and capture range as a function of input amplitude.An emitter follower has been added to the normal VCOoutput to prevent pulling the loop off frequency.CIRCUIT DIAGRAM+18FREQUENCY METER WITHLOW-COST LAMP READOUTl-l00mVp-pINPUT U--_-fl------tVCOOUT47lKFigure 8-61aINPUT 0---1100-1000mVrms~0.13fS.I~ 0.13fS-...JI-------~--~~~ ,~--~~--IONFREQUENCY~ FREQUENCYI BOTH UNITS "ON"I AT OVERLAPSENSINGFREQUENCY fsFigure 8-60INPUTAMPLITUDE(mV(p-p))1005040302010LOCK RANGE VS INPUT AMPLITUDE10.004\I\.\ /\ /I1\\/III /I.IIIII1:10.005 10.006 10.007 10.008FREQ. (MHz)Figure 8-61bVII(61

PHASE LOCKED LOOP APPLICATIONSRAMP GENERATORS (566)Figure 8-62 shows how the 566 can be wired as a positiveor negative ramp generator. I n the positive ramp generator,the external transistor driven by the pin 3 output rapidlydischarges C1 at the end of the charging period so thatcharging can resume instantaneously. The pnp transistorlikewise rapidly charges the timing capacitor C1 at the endof the discharge period. Because the circuits are reset soquickly, the temperature stability of the ramp generator isexcellent. The period T is 1/2fo where fo is the 566 freerunningfrequency in normal operation. Therefore,1 RTC1V+7 = - =2fo 5(V+ - V c)where V c is the bias voltage 7 pin 5 and RT is the totalresistance between pin 6 and V+. Note that a short pulse isavailable at pin 3. (Placing collector resistance in serieswith the external transistor collector will lengthen thepulse.)SAWTOOTH AND PULSE GENERATOR (566)Figure 8-63 shows how pin 3 output can be used toprovide different charge and discharge currents for C1 sothat a sawtooth output is available at pin 4 and a pulse atpin 3. The pnp transistor should be well saturated topreserve good temperature stability. The charge anddischarge times may be estimated by using the formulaRTC1V+7 =5(V+ - Vc )where RT is the combined resistance between pin 6 andV+ for the interval considered.v+POSITIVE SAWTOOTH ANDPULSE GENERATORNEGATIVE RAMP GENERATORv+1.5K1.5Kvc10K,....&..--...... I--I--~A/'v SAWTOOTH~PULSEvc10KFigure 8-63aFigure 8-62aPOSITIVE RAMP GENERATORv+NEGATIVE SAWTOOTH ANDPULSE GENERATORv+20K1.5K1.5K5 6 8 4566~TOOTH4.7K10K~LSE22KFigure 8-62bFigure 8-63b62

PHASE LOCKED LOOP APPLICATIONfTRIANGLE-TO-SINE CONVERTERS (566)Conversion of triangular wave shapes to sinusoids isusually accomplished by diode-resistor shaping networks,which accurately reconstruct the sine wave segment bysegment. Two simpler and less costly methods may be usedto shape the triangle waveform of the 566 into a sinusoidwith less than 2% distortion_The first scheme (Figure 8-64al uses the non-linearlOS - VOS transfer characteristic of a p-channel junctionFET to shape the triangle waveform. The second scheme(Figure 8-64b) uses the non-linear emitter base junctioncharacteristic of the 511 B for shaping.In both cases, the amplitude of the triangle waveform i$critical and must be carefully adjusted to achieve a loWdistortion sinusoidal output. Naturally, where addition~1waveform accuracy is needed, the diode-resistor shapi'19scheme can be applied to the 566 with excellent result$since it has very good output amplitude stability whenoperated from a regulated supply.+12VFET TRIANGLE·TO-SINE CONVERTER25KAMPLITUDEADJUST1001%SQUAREWAVEOUTPUT.JLFigure 8-64a+12VTRIANGLE·TO-SINE CONVERTER2KRl10KSINEOUTPUTS(\J.001"F6 85 456610K200 47KL.------..... -----..-4--

PHASE LOCKED LOOP APPLICATIONSSINGLE TONE BURST GENERATOR (566)Figure 8-65 is a tone burst generator which supplies a tonefor one-half second after the power supply is activated; itsintended use is as a communications network alert signal.Cessation of the tone is accomplished by the SCR, whichshunts the timing capacitor C1 charge current whenactivated. The SCR is gated on when C2 charges up to thegate voltage, which occurs in 0.5 seconds. Since only 70llAare available for triggering, the SCR must be sensitiveenough to trigger at this level. The triggering current can beincreased, of course, by reducing R2 (and increasing C2 tokeep the same time constant). If the tone duration must beconstant under widely varying supply voltage conditions,the optional Zener diode regulator circuit can be added,along with the new value for R2, R2 = 82K.If the SCR is replaced by a npn transistor, the tone can beswitched on and off at will at the transistor base terminal.I.SK10KFREQUENCY MODULATED GENERATORFOR SMALL DEVIATIONS (TO ±20%)+VMODULATIONFREQUENCYADJUSTLOW-PASS FILTER ORSINE CONVERTER MAYBE INSERTED HERE+VCENTER r---.,.---iFREQ.ADJUST10KIF SINUSOIDAL MODULATIONIS REQUIREDFigure 8-66/VSINGLE BURST TONE GENERATOR+12VFREQUENCY MODULATED GENERATORFOR LARGE DEVIATIONS (TO ±100%)+V+VI.SK. 001RlMOD.FREO .ADJ.CENTERFREO.ADJUSTVc+12V+12V10K·~h"'82K180KI C 2OPTIONAL "::" -::- so -::-MFDREGULATEDCAPACITORCHARGING CIRCUITSCRJTONE FREQ. ~IO.S SEC TONEBURST FOLLOWING1 APPLICATION OF POWER:lR,c,20KR C2I C1~K~j----J ~_ _ DEVIATION- - ADJUSTLOW-PASS FILTER OR SINE CONVERTERMAY BE INSERTED HERE IF SINUSOIDALMODULATION IS REQUIREDrFigure 8-65Figure 8-67LOW FREQUENCY FM GENERATORS (566)Figures 8-66 and 8-67 show FM generators for lowfrequency (less than 0.5MHz center frequency) applications.Each uses a 566 function generator as a modulationgenerator and a second 566 as the carrier generator.Capacitor C1 selects the modulation frequency adjustmentrange and C{ selects the center frequency. Capacitor C2is a coupling capacitor which only needs to be large enoughto avoid distorting the modulating waveform.If a frequency sweep in only one direction is required, the566 ramp generators given in this section may be used todrive the carrier generator.RADIO FREQUENCY FM GENERATORS (566, 560B)Figure 8-68 shows how a 5608 may be used as a FMgenerator with modulation supplied by a 566 functiongenerator. Capacitor C1 is chosen to give the desiredmodulation range, C2 is large enough for undistortedcoupling and C3 with its trimmer specifies the centerfrequency. The VCO output may be taken differentiallyor single ended.A 5618 or 5628 with appropriate pin numbering changesmay also be used in this application. If a sweep generatoris ~esired, the 566 may be connected as a ramp generator(described elsewhere in this chapter).64

PHASE LOCKED LOOP APPLICATIONSRF-FM GENERATORDESIGN IDEAS FOR USING PHASE LOCKEDLOOPS+ 18MODULATIONFREQUENCYLOW-PASS FILTERIF REQUIREDThe following design ideas were drawn mainly from theSignetics-EDN Phase Locked Loop Contest. These circuitsshould be viewed as design suggestions only since Signeticshas not verified their operating characteristics. I n all cases,however, the principle of operation appears to be sound.Quotation marks indicate quotes taken directly from thecontest entry.10KCENTERFREQ. ADJ.AIRCRAFT VHF OMNIDIRECTIONAL RANGE (VOR)RECEIVERFigure 8-68PRECISION POWER INVERTER (566,540)Figure 8-69 shows a precision 12 VDC to 115 V AC 100Winverter. Its triangular output is derived from the 566function generator, providing a high degree of frequencystability (±.02%/oC). The 540 power driver is used todrive the power output stage. Because of third harmonicattenuation in the transformer, the output is very close toa pure 60Hz sine wave.Herbert F. Kraemer of Minneapolis, Minnesota, submittedthe winning contest entry which uses one phase lockedloop (562) as an AM detector, a second loop (565) as anFM detector and a third loop (565) as a self-biased phasedetector."The circuit is a new type of VOR (VHF omnidirectionalrange) receiver used in air navigation to determine anairplane's angular bearing with respect to a VOR transmitterlocated on the ground. The principles of the circuitallow any desired increase in accuracy, as compared tocurrent units, with potential cost savings.PRECISION 100 WATT POWER INVERTER+12V87+10 +2.2 566Figure 8-6965

PHASE LOCKED LOOP APPLICATIONSA VOR station transmits in the VHF band (108-117.9MHz). Two signals are transmitted on the samecarrier, i.e.,1 ) A 30Hz reference signal which frequencymodulates an audio frequency subcarrier of9960Hz. This subcarrier then amplitude modulatesthe VHF carrier.2) A 30Hz directional signal which amplitudemodulates the VHF carrier.The latter signal varies in phase with respect to thereference, depending on the bearing of the VOR stationand the receiver. Both signals are in phase when the receiveris north of the transmitter and 180 degrees out of phasewhen the receiver is south.Current VOR receivers are specified to be accurate withina 1-2 degree bearing, but many pilots accept 4 degreeerrors. The major design problem is to produce a receiverwhich will measure phase differences to an accuracy ofabout 1 degree, throughout the entire 360 degree range."Although analog quarter-square multipliers can be built toan accuracy of 0.01%, the simpler analoq phase detectorsare only accurate to 3-4 0 . This circuit uses the NE562PLL to frequency multiply the two 30Hz signals, producing60 and 120Hz signals. A digital method com bines thesesignals, thereby dividing the entire range of bearings intoeight 45 0 sectors. One of eight lights on the display willlight, showing the pilot his approximate bearing. An analogmethod .is then used to further determine the phasedifference and the bearing within the given 45 0 sector.Extending the principle further, sectors of 22%0 could beused for improved accuracy.This VOR receiver does not have the conventional to-fromswitch since it indicates directly throughout the entire360 0 range. Confusion of 180 0 in bearing (going the wrongway) is impossible with this receiver.System Description (References to Block Number -Figure 8-70)Block 1.Block 2.Block 3.Block 4.Block 5.Block 6.Block 7.BI·ock 8.Block 9.This is a standard VHF tuner.The NE561 is used for IF and AM detection.A low pass filter removes the 9960Hz subcarrier.It appears that a zero crossing detectoris not needed to shape the input signal to theNE562.Frequency multiplier.High pass filter.FM detection of 30Hz signal.A calibration adjustment to compensate forany phase shifts throughout the circuit. A gainmay be needed since the FM detector output islow.Another frequency multiplier.Standard ripple flip-flops for divide-by-two.Block 10.Block 11.Block 12.A null principle is normally used in a VORreceiver so that the pilot can fly al~ng apredetermined course, nulling the needle byturning his plane. To insure that the needlealways reacts in the same direction for a givendirection of error, even sectors are treateddifferently than odd sectors." The phase comparisonis made with respect to C for oddsectors, and with respect to C for even sectors.II At the desired nUll, the two signals must be90 degrees out of phase to obtain a zero outputfrom the phase detector. Some gain may beneeded to compensate for the losses in Block10.The phase detector portion of the N E565 onlyis used. The VCO part is unused but may bevaluable in certain types of special displays.An alternate form of analog phase detectormight be an AND gate followed by a standardduty cycle integrator, such as used on dwellmeters.Block 13. The digital signals from the flip-flops aredecoded with AND gates to indicate the sectorcorresponding to the phase lag between thetwo 30Hz signals."SPEECH PRIVACY CIRCUIT (SPEECH SCRAMBLER)The second place en.try was that of David M. Alexander ofAustin, Texas. His application for the loop was a voicescrambler-unscrambler for private communications."This circuit utilizes the principles of frequency inversionand masking to render speech unintelligible to listeners notpossessing a similar unit. A synchronization signal isgenerated as part of the scrambled signal which phase locksthe decoding carrier oscillator to the coding oscillator andthus guarantees minimum distortion in the unscrambledspeech. This synch signal also increases the security close tothe inversion point where they are displaced only slightlyfrom their original values.In operation, a single circuit serves as both scrambler andunscrambler at one end of a two-way communications link.It is switched from the receive mode to the transmit modeby a multipole relay controlled by the push-to-talk switchon the system microphone or handset.As can be seen by the diagram (Figure 8 -71), the majorcomponents of the system are the synch oscillatorPLL-1 (NE560B), the carrier oscillator-modulator PLL-2(NE561 B) and the mixer-gain stage OA-1 (5709).66

PHASE LOCKED LOOP APPLICATIONSVHF OMNIDIRECTIONAL RANGE (VOR) RECEIVER30HzDIRECTION SIGNAL30HzREF. SIGNAL 9960Hz SUBCARRIERFFI*r30HzI-,----FF..60HzFREQUENCYMULTIPLICATIONOFREFERENCE SIGNALFF120Hz30Hz60Hz120 HzAB+vCA'DIGITAL SIGNALSB'C'DISPLAYMETER0_45°CPHASE ADJ.PHASE DETECTORNE56512METERZERO1090°C PHASE ADJ.GAIN ADJ. AND LIMITAB(90-135°C)(135-180°C)0_45°C KNOB ON DISPLAY NULLSMETER FOR INTERPOLATIONCA'B'C'(180-225°C)(225-270°C)(270-315°C)(315-360°C)Figure 8-70SIMPLIFIED DIAGRAM OF VOICE SCRAMBLERR---0TINPUTRCoOUTPUT GAINTI1.5KHz LOW PASSFigure 8-7167

PHASE LOCKED LOOP APPLICATIONSIn the transmit mode, PLL-1 is adjusted to free-run at theinversion frequency (105kHz), or Y2 the desired carrierfrequency. PLL-2 is phase locked to this oscillator andoperates on its second harmonic frequency (3kHz). Theaudio to be scrambled is applied to the input of themultiplier of PLL-2. This produces the sum and differenceproducts of the input audio and the encoding carrier. Thesum product is filtered out by the low pass filter (Lx-Cx),leaving only the difference product. This product consistsof the original audio signal with the frequency componentsinverted about Y2 the carrier frequency, or 1.5kHz. Thesquare wave output of the oscillator of PLL-1 is low passfiltered by network Ly-Cy to produce a sine wave syncsignal which is mixed with the inverted speech by OA-1to produce the final scrambled signal.In the receive mode, PLL-1 is phase locked to the 1.5kHzsynch and masking signal and acts as a signal conditionerfor this signal. PLL-2 doubles this frequency to producethe decoding carrier. The scrambled signal is notch-filteredby network Lz-Cz to remove the 1.5kHz .:synci and maskingsignal and the resultant inverted audio applied to themultiplier of PLL-2. Here it is re-inverted in a mannersimilar to that of the transmit mode. The resultantunscrambled audio is amplified in OA-1 for output tofurther system audio stages."[Note: It is suggested that the 1.5kHz "sync and masking"signal be changed to 1.0kHz, since PLL-2 (free-running at3kHz) will lock to the third harmonic of the 1 kHz squarewave from PLL-1 more readily than to the small secondharmonic of the 1.5kHz signal. It may then be desirableto disconnect the notch filter during transmission. Ofcourse, the filters may be implemented using active filtertechniques.]PRECISION PROGRAMMABLE TIME DELAYGENERATORSam Butt of Gaithersburg, Maryland, submitted the thirdplace entry. This circuit provides both a pulse and a highfrequency output at some time td after an input pulse isreceived. The interval td is programmable in 10 steps bymeans of a digital output switch.Figure 8-72 shows the circuit in simplified form. It worksas follows:The 562 VCO is set so that its center frequency is at a pointslightly above (say 10.5MHz) the window of the 10MHzband pass filter (BPF). Thus, no rf appears at the output.When a pulse is received at the input, the flip-flop is set soas to actuate one input A of the N8880A NAND gate.The other side of the NAND gate B receives a signal whichoccurs at the rate of frlM where M is set by the binaryoutputswitch. The output of the NAND gate begins todrive the N8291 A binary ripple counter which is connectedto the divide-by-N drcuit in the loop feedback path. When10 counts have been registered, the divide-by-N counter isputting out fo/10 or (in the assumed case) 1.05MHz.Since the phase comparator now sees two frequencies veryclose together, the ~oop locks up and fo = 10f r .Sincef r is1 MHz, the VCO operates at 10MHz rf which the band passfilter passes to the output. This rf is detected and used toreset the input flip- :Iop and the counter in preparation forthe next input pulse. The duration of the rf output isdetermined mainly by the detector time constant. Theduration of the output pulse, which begins when the rfdetector actuates the one-shot, is determined by theone-shot time const mt.The delay time iswhere M is settabL' between 1 and 10 using the digitalswitch.METAL DETECTOR USING PLL AS A FREQUENCYMETER (565)The metal detector shown in Figure 8-73 was submittedto the Signetics-EDN Phase Locked Loop Contest byJim Blecksmith of Irvine, California. It incorporates a 565as a frequency meter which indicates the frequency changein a Colpitts oscillator whose tank coil approaches a metalobject. The loop output voltage at pin 7 is compared withthe reference voltage at pin 6 and the difference amplifiedby meter amplifier 04, 05'To increase the loop output (pin 7) to about O.5V perpercent of frequency deviation, a current source (Q2, Q3) isused to supply most of the capacitor (2.5mA) charge anddischarge current at pin 8. The 20K resistor connected toO.5Vpin 8 changes the charge and discharge current by -- =20Kn.025mA or about 1 % per O.5V. Since the voltage at pins 8and 7 track, the loop output voltage is also O.5V perpercent deviation. (This technique of increasing loopoutput swing for small frequency deviations is discussedin the Expanding Loop Capability section of this chapter.)I ncreasing oscillator frequency, as indicated by a risingmeter indication, results when the search coil is broughtnear a non-ferrous metal object. Reduced oscillatorfrequency, as indicated by a dropping meter reading, resultsfrom the search coil being brought near a ferrous object.68

PHASE LOCKED LOOP APPLICATIONSPRECISION PROGRAMMABLE TIME DELAY GENERATOR.001

PHASE LOCKED LOOP APPLICATIONSPROGRAMMED PHASE OR FREQUENCY SHIFTHoward E. Clupper of Chadds Ford, Pennsylvania, submittedthe following circuit in which Ita digital phaseshifter is inserted in the loop between the VCO and thephase comparator. The phase shift is programmed bysequentially selecting the ring counter outputs by means ofthe multiplexer and up-down counter."As shown in Figure 8-74, the eight ring counter outputsare separated by 45 0 , which is within the lock-in range ofthe loop. Output 1 is constrained to follow the phaseshift introduced and may be used, for example, to drive asynchronous motor above or below its normal speed, whilestill maintaining reference with the input. This is accomplishedby monitoring the contents of the up-downcounter (which may be any length). As long as the counterdoes not overflow, the motor may be advanced or retardedin any manner and then returned to the original relationshipwith respect to the 60Hz reference input by runningthe UfO counter to the initial value.For higher frequency outputs, a divide-by-N counter maybe added in the normal manner and the output takendirectly from the VCO at output 2. Operation in thismode would provide means to generate a preciselycontrolled FM signal of any arbitrary center frequencydepending upon the frequency of the reference input andthe value of N."The 565 may be used in this circuit in place of the 562 forlower frequency applications (less than 500kHz).PROGRAMMED PHASE OR FREQUENCY SHIFTER60HZ'~'" ON,"' ~r------------------- -- -----------I12 13 14",COMP.L.P. FILTERVCO- - --,IIOUTPUT-2I 1115I1.. ___ _r8-STATE TWISTED RING COUNTERI II +N I, ,~- -..L __J-,~--------.---------~----------~~--~ II OUTPUT-l1---+---1._--0 60 ± ~ HZSINGLE -.Jb45° STEP IIPHASESYNCH,.......t-.......... ....Io...y-L l_L,ADD'LCAPACITY ,...... --.;;.---,r--- - - ___ J8-INPUT MULTIPLEXERIN8230RING COUNTER WAVEFORMSA~B~C~D~A~- IB~c~ID~IFigure 8-7470

PHASE LOCKED LOOP APPLICATIONSFSK DATA CONVERTER FOR CASSETTE RECORDERA circuit scheme which ablows an ordinary reel or cassettetape recorder to be used as a digital data recorder wassubmitted by Daniel Chin of Burlington, Massachusetts."The circuit design allows any single-track audio taperecorder with frequency response to 7kHz to be used as adigital recorder for many non-critical applications. Thisapplication provides a complete data recording systemusing two recorded frequencies on a single track. Thetwo frequencies are obtained from two synchronizedN E565s. Detection of the recorded frequencies requires athird N E565. A fourth circuit is used to generate andsynchronize the system clock. The advantages obtained byusing these techniques are elimination of the need for:1.2.A timing channel to strobe off the data, orA third frequency for null, while using theother two frequencies for 1 and O.This implementation, therefore, is one of the simplest waysto get a digital recording system on an audio recorder. It isshown in block diagram form in Figure 8-75.The parameters chosen for the circuit design allow a digitalrecording bit rate of 800Hz or 100 8-bit characters persecond. Though 100 characters per second is less than the300-character-per-second speed of a high-speed paper tapereader, the low cost of this circuitry combined with theaudio tape recorder should make this system very attractivefrom a cost performance viewpoint. This is especially truewhen compared with the normal Teletype speed of 10characters per second.BLOCK DIAGRAM OFPLL CASSETTE RECORDERThe circuits will also work with the readily available lowcost cassette recorders now available, which make compactas well as low cost information storage. A FSK system ofrecording is used, which allows the voice recording andreproduction electronics of the recorder to be unmodifiedfor use in recording digital information. The retainedelectronics may also be used to record voice messageidentification of the various sections of the tape.The intended use of this circuit is to convert an audiorecorder for minicomputer programs written for engineeringdesign applications. Such an application requiresgood information storage and retrieval over a wide range ofstorage time. Redundancy may be incorporated by using atwo-channel recorder (stereo) and a FSK detector perchannel. The outputs of the two detectors could then beo Red digitally to recovered recorded 1 sand, thus, givea safeguard against dropouts.Circuit DescriptionFour NE565s are used in three circuits to achieve thedesign. These are:The FSK detector (Figure 8-76a) is used to detect 6.4kHzfor a 1 and 4.8kHz for a O. The data output is taken from a5711 connected to pins 7 and 6 of the N E565. Therecording method used is RZ FSK, which means that a zerois recorded as 4.8kHz for the entire bit period and one isrecorded as 6.4kHz for about 60 percent of the period and4.8kHz for the remaining 40 percent of the period. This60 percent bit duty cycle insures that the clock willsynchronize with a negative transition during the time thata 1 should be detected.CASSETTE RECORDER FSK DETECTOR,CLOCK GENERATOR AND FSK GENERATOR+5VADJUSTFOR 5,6KHzWITH INPUT 0,5K,03PLAYBACKTAPERECORDERRECORD800HzI--..... --CLOCKIN 4454UKINPUT o-_~rI-'l1N'0Kv--1-1~13""1) r-I+12V.... ------1,25mS-1DATA IN~I ° ~I-DATAI-l rFROMRECORDERlK-5VTO CLOCK'--------0 GENERATOR~-{J~~-RECORDED FSKOUTPUT ON PI N 7Figure 8-75Figure 8-76a71

PHASE LOCKED LOOP APPLICATIONSThe clock generator (Figure 8-76b) is used to derive the800Hz with no input. When the data pulses are extractedfrom the recorded data, the clock is synchronized to thedata. The design allows up to 7 zeros in succession withoutcausing the clock to go out of synchronization. Thiscondition is easily met if odd parity is used to record the8-bit characters. (One of the 8 bits is a parity bit and, thus,one bit out of 8 is always a one.)The FSK generator (Figure 8-76c) provides the FSK signalfor recording on tape. It consists of 2 oscillators locked tothe basic 800Hz system clock but oscillating at 6.4kHz and4.8kHz. The incoming data to be recorded selects eitheroscillator as the frequency to be recorded. Harmonicsuppression of the square wave output is taken care ofautomatically by the high frequency roll off characteristicof the tape recorder."CLOCK GENERATORSET FORBOOHzWITH NO INPUT5K+5V2.0SELF-RESETTING DIGITAL CLOCKThe following application, submitted by Don Lancaster ofGoodyear, Arizona, makes use of the 561 B as a 60kHz AMdetector.liThe 561 B Phase Lock Loop may be combined with TTLintegrated circuits to form an always-accurate digital clockbased upon the monitoring and direct display of the timecode provided by NBS radio station WWVB operating at a60kHz carrier frequency. Unlike the other time services,WWVB presents a time code directly in BCD digital form,coded as a 10 decibel AM reduction of the carrier. A clockbased on this time code information would always beaccurate as no counters would be involved and the digitaldisplay would always correct itself after a power failure,unlike regular electric clocks which must be manually reset.Until recently, this type of clock circuitry would have beenprohibitively expensive, but now the PLL makes thereceiver portion of the_ clock extremely simple, while recentdrastic price reductions in TTL MSI make the display andreadout also a simple and relatively economical proposition.I.BK.00110 76 N.C ...........---....---(') OUTPUTBOOHzBLOCK DIAGRAM OF SELFRESETTING DIGITAL CLOCKTOFSK-5Vn r-:-1 r-::-1 n OUTPUT~ 1 U 1 ~FROM 5710-u-u-LFLJ BOO Hz CLOCKFigure 8-76bFSK GENERATOR+5VFROMCLOCKSET FOR6.4KHz5KI.BK.001107.03_ll.23ms r-OATA IN~OGENERATORSET FOR 4.BKHzFSK TOI.BK.001RECOROERFigure 8-772 BFigure 8-76cFigure 8-71 shows a block diagram of the system. A highQ antenna and a suitable low noise preamplifier are used fora front end, followed by an additional gain stage and the561 set up as a synchronous AM detector. The output ofthe 561 consists directly of the demodulated time code.72

PHASE LOCKED LOOP APPLICATIONSThe code is then translated with a comparator and routedto a two-monostable synchronizer that seeks the doubleonce-each-minute sync pulse that identifies that thetens of hours code will follow (Figure 8-78). Aftersynchronization, the code is "1"-"0" detected and routedto a five stage shift register. On every fifth count (consistingof a BCD word and a marker) one of four quad latches arestrobed. The latches then store the appropriate minutes,tens of minutes, hours and tens of hours. Each quad latchthen drives a BCD/Decimal Decoder/Driver, which in turndrives a N I XI E® or other suitable display tube.CHART OF TIME CODE TRANSMISSIONS FROM WWVBTIME10 20 SECONDS- REFERENCE TIME0.2 SECOND-BINARY "ZERO"-/ I ~"REFERENCE MARKER FOR MINUTES- - (TYPICAL)SIGNAL ---10.8 SECONDS II"ON"SIGNAL-lOdBPl40 20 10 20 10MINUTES SETHOURS SETI I Ii!= SECOND-BINARY "ONE"I-1 .0 SECOND-I I (TYPICAL)I (TYPICAL)20 30 40 SECONDS.r--""'II~"200 100 80 40 20 10ADDADDDAYS SETTIME AT THIS POINT EQUALS 258 DAYS, 18 HOURS,42 MINUTES, 35 SECONDS, TO OBTAIN THECORRESPONDING UT2 SCALE READING,SUBTRACT 41 MILLISECONDS. ___________...JUT2RELATIONSHIP40I50I60 SECONDS10.8 SECOND POSITION IDENTIFIER(TYPICAL)P4P5800 400 200 10080 40 20UT2 SETDIFFERENCE OF UT2 FROMCODED TIME IN MILLISECONDSGROUP 12MARKER:-lU_PULSEPOSITION MARKERAND PULSEillPERIODIC UNCODEDMARKER AND PULSEnlJlUNCODED MARKERAND PULSEBINARY "ONE"BINARY "ZERO"NBS TIME CODEFORMAT "WWVB"1 ppsCODEFigure 8-787:t

PHASE LOCKED LOOP APPLICATIONSThe display gives the time to the nearest minute and isupdated every minute. Seconds are added simply by ablinker, or else a divide-by-60 counter and decoder drivermay be used. This counter may be reset every minute bythe sync pulse; thus, after a power failure, the clock wouldcorrect its seconds reading within a minute of the powerbeing reapplied. If desired, the day of the year may besimilarly displayed and if local time is preferred to GMT, asuitable BCD adder or subtractor may be placed betweenthe shift register and the latches.Figure 8-79 shows the PLL detector circuit. It was foundthat either a roOftop hula hoop or a ferrite rod and a local10dB gain amplifier was sufficient to drive the PLL if asingle transistor gain stage was added between the two. Theamplified 60kHz signal is applied directly to the R F inputand applied to the AM Multiplier input via a 90 0 phaseshift network. The output of the multiplier is triply RCf'iltered to give a good rejection of 60Hz hum, while stillallowing the 0.2 second minimum-width pulses to passwith good fidelity."PLL PORTION OF SELF·RESETTING DIGITAL CLOCK+18V3KFINETUNING+18V16 15 14 13 12 11 10 9NE561B+18V (TOP VIEW)4:JK5K-=-60 KHzWWVB 8.2K 8.2KTIME CODEFROM PREAMP~+OUTPUTI11lF~F ±F TO-=- COMPARATOR-=- -=-Figure 8-79TAPE RECORDER FLUTTER METERUsing the 561 as a flutter meter for tape recorders wassuggested by Ronald Blair of Houston, Texas. His circuit isgiven in Figure 8-80."The Signetics PLL 561 B is used to detect the frequencyvariations of the playback 3kHz tone. The VCO frequencyis set to a nominal 3kHz by Co and fine tuning trimmer.The demodulated output is ac coupled to a high inputimpedance amplifier. An oscilloscope can be used tomeasure peak deviations and a true R MS voltmeter is usedto make RMS flutter readings. Note: Waveform is complexand averaging or peak reading meters will not give truereadings.The output may be calibrated by feeding in a 3kHz tonefrom an oscillator and offsetting the frequency by 1 % andmeasuring the output level shift. Good recorders have RMSflutter of less than 0.1 %. The output can be filtered tostudy selected frequency bands.Speed variations in the movement of tape across theheads in a 4 tape recorder cause the playback frequency tovary from the original signal being recorded. These speedvariations are caused by mechanical problems associatedwith the tape drive and tape guidance mechanisms. Thevariation in frequency of the playback signal is calledflutter and is generally measured over a frequency range of0.5Hz + 0.200Hz.Test tapes with low recorded flutter variations areavailable to test playback mechanisms. These tapes arestandardized at 3kHz. With systems equipped with recordheads, a 3kHz tone can be recorded for analysis."[Note: A 565 may be used in place of the 561 B since thefrequency is quite low.]74

PHASE LOCKED LOOP APPLICATIONSFLUTTER METER USING 5618+18V,~-.JR·::::1 ....----,HEADTAPE MOTIONFigureS-SOPHASE LOCKED LOOP FLUID FLOWMETERWhenever a phase locked loop is locked, its VCO signal is90 0 out of phase with the input signal (unless the inputsignal is off frequency and very weak). It has been foundthat the loop can lock to itself if its VCO signal is phaseshifted 90 0 and then applied to the input. The loop willthen run at whatever frequency develops a 90 0 phase shiftin the phase shift network. An interesting application ofthis technique was submitted by Richard E. Halbach ofMilwaukee, Wisconsin. Mr. Halbach used the time delay ofa mass (bolus) of fluid moving through a length of tubingas a phase shift mechanism so that the PLL frequencybecame a function of the flow rate. Figure 8-81 showsthis technique in block diagram form (a) and implementedusing a 5608 (b)."Simply stated, Nuclear Magnetic Resonance (NMR) isthat precession of nuclei, in this case hydrogen, in thepresence of a magnetic field. Its precession can be detectedby an appropriate receiver coil assembly. A coil up-streamfrom the receiver coil when activated changes the nuclearmagnetization of a bolus (or mass) of fluid in such a waythat this change can be detected in the receiver as the bolussubsequently passes through it ... transport delay from thetag coil to the receiver, an inverse function of flow velocity,can be used to introduce a 90 0 phase lag into the externalfeed back loop of the PLL, which when matched with the90 0 internal lag of the PLL, allows the loop to lock. TheVCO frequency is then a direct function of velocity offlow."[Note: A 565 can be used as well as the 560 at this lowfrequency. Frequency can be read out at the low pass filter(using a low frequency integrating voltmeter) or bymeasuring the period of the output waveform (flow is theninversely related to the period). If the VCO is run at acarefully chosen higher frequency and then divided downprior to the phase detector and tag coil, the frequency ofthe VCO as read by a counter can be adjusted to indicatein flow units directly.]PHASE LOCKED LOOP FLUID FLOW METERPHASE LOCKED LOOP FLUID FLOW METER+18V200MFD1V (P-P) INPUT FROM...-----+:-It---o RECEIVER DETECTOR+18V16C1100MFDNON-POLARC2270MFDNON-POLARPLL 560BFLUID FLOWC1 WAS CHOSEN FOR STABLE LOOP OPERATIONR1C2 DETERMINES OPERATING FREQUENCY RANGE OF 1-3HzQ1 Q2 Q3 FORM DIFFERENTIAL OUTPUT AND DRIVE FOR TAG CIRCUITRYFigure S-S1aFigure S-Slb75

PHASE LOCKED LOOP APPLICATIONSREFERENCES1. deBeliecize, H., "La reception synchrone," OndeElectron., vol. II, pp. 230-240, June 1932.2. Gardner, F. M., Phaselock Techniques, New York:Wiley, 1966.3. Grebene, A. B., and Camenzind, H. R., "Frequencyselective integrated circuits using phase lock techniques,"IEEE J. Solid-State Circuits, vol. SC-4, pp. 216-225,Aug. 1969.4. Moschytz, G. S., "Miniaturized RC filters using phaselockedloop," Bell System Tech. J., vol. 44, pp. 823-870,May 1965.5. Viterbi, A. J., Principles of Coherent Communication,New York: McGraw-Hili, 1966.6. Mattis, J. A., "The Phase Locked Loop - Acommunication system building block", Broadcast Engigineering,Feb. 1972.7. Grebene, A. B., "A monolithic signal conditioner/synthesizer," NEREM Record, vol. 12, pp. 60-61, Nov.1970.8. Chu, L. P., "Phase·locked AM radio receiver," IEEETrans. Broadcast and Television Receivers, vol. BTR-15,pp. 300-308, Dec. 1969.9. Mattis, J. A., and Camenzind, H. R., "A new phaselockedloop with high stability and accuracy," SigneticsCorp. Appl. Note, Sept. 1970.76

PHASE LOCKED LOOP APPLICATIONSSALES OFFICES• New England Regional Sales Office: Miller Building, Suite 11594 Marrett Road, Lexington, Massachusetts 02173Phone (617) 861-0840 TWX: (710) 326-6711• Atlantic States Regional Sales Office: 2460 Lemoine Ave., Fort Lee,New Jersey 07024Phone: (201) 947-9870 TWX: (710) 991-9794-Florida: 3267 San Mateo, Clearwater 33515Phone: (813) 726-3469 TWX: (810~ 866-0437Maryland: Silver SpringsPhone: (301) 946-6030Pennsylvania and Southern New Jersey: P. O. Box 431, CedarBrook Bldg., Tauntan Rd., Medford, New Jersey 08055Phone: (609) 665'5071Virginia: 12001 Whip Road, Reston 22070Phone: (301) 946-6030• Central Regional Sales Office: 5105 Tollview Drive, Suite 209Rolling Meadows, Illinois 60008Phone: (312) 259-8300 TWX: (910) 687-0765Minnesota: 7710 Computer Ave., Suite 132, Minneapolis 55435Phone: (612) 922-2801 TWX: (910) 576-2740Ohio: 3300 So. Dixie Drive, Suite 220, Dayton 45439Phone: (513) 294-8722• Northwest Regional Sales Office: 811 E. Arques,Sunnyvale, CA 94086Phone (408) 739-7700 TWX: (910) 339·9'220 (910) 339·9283• Southwest Regional Sales Office: ?o061 Business Center Dr.Suite 214, Irvine, Ca 92664Phone: (714) 833'8980, (213) 924·1668 TWX: (910) 595·1506Arizona: 4747 No. 16th St., Suite 0·102, Phoenix 85016Phone: (602) 265·3153California: P. O. Box 788, Del Mar 92014Phone: (714) 453·7570REPRESENTATIVESALABAMAHuntsville 35801: Compar Corp., 904 Bob Wallace Ave., Suite APhone: (205) 539·8476ARIZONAScottsdale 85252: Compar Corp., Box 1607Phone: (602) 947·4336 TWX: (910) 950·1293CALIFORNIASan Diego 92123: Celtee Company, Inc., 8799 Balboa AvenuePhone: (714) 279·7961 TWX: (910) 335-1512CANADAToronto 17, Ontario: Corning Glass Works of Canada, Ltd.,135 Vanderhoff Ave.Phone: (416) 421·1500 TWX: (610) 491·2155Montreal 265, Quebec: Corning Glass Works of Canada,7065 Chester Ave.COLORADODenver 80237: Parker Webster Company, 8213 E. Kenyon Dr.Phone: (303) 770·1972CONNECTICUTHamden 06518: Compar Corp., P. O. Box 5204Phone: (203) 288·9276 TWX: (710) 465·1540FLORIDAAltamonte Springs 32701: WMM Associates, Inc., 515 Tivoli Ct.Phone: (305) 831-4645Clearwater 33516: WMM Associates, Inc., 1260A S. Highland Ave.Phone: (813) 446·0075Pompano Beach 33060: WMM Associates, Inc.,721 South East 6th TerracePhone: (305) 943·3091INDIANAIndianapolis 46250: R. H. Newsom Associates, 6320 Woburn Dr.Phone: (317) 849·4442MARYLANDSilver Springs 20904: Mechtronics Sales, Inc., 11700 Old ColumbiaPike, Suite L·6 Phone: (301) 622·2420. MASSACHUSETTSNewton Highlands 02161: Compar Corp., 88 Needham StreetPhone: (617) 969·7140 TWX: (710) 335·1686MICHIGANGrosse Pointe Park 48230: Greiner Associates, Inc.,15324 E. JeffersonPhone: (313) 499·0188, (313) 499·0189 TWX: (801) '221·5157MINNESOTAMinneapolis 55416: Compar Corp., P. O. Box 16183Phone: (612) 922-7011MISSOURISt. Louis 63141: Compar Corp., 11734 Lackland Industrial DrivePhone: (314) 567·3399 TWX: (910) 764·0839UPSTATE NEW YORKDewitt 13214: TriTech Electronics, Inc.,P. O. Box C Phone: (315) 446-2881NORTH CAROLINAWinston-Salem 27101: Compar Corp., 1106 Burke StreetPhone: (919) 723·1002 TWX: (510) 931·3101OHIODayton 45405: Compar Corp., P. O. Box 57, Forest Park BranchPhone: (415) 435·1301Fairview Park 44126: Compar Corp., P. O. Box 4791Phone: (216) 333·4120 TWX: (810) 421·8396TEXASRichardson 75080: Semiconductor Sales Associates,312 North Central Expressway, Suite 213Phone: (214) 231-6181WASHINGTONBellevue 98009: Western Technical Sales, P. O. Box 902Phone: (206) 454-3906 (503) 224·5107 TWX: (910) 443·2309DISTRIBUTORSARIZONAPhoenix 85009: Hamiiton/Avnet Electronics, 1739 N. 28th Ave.Phone: (602) 269-1391 TELEX: 667·450CALIFORNIABurbank 91504: Compar Corp., 2908 Naomi AvenuePhone: (213) 843-1772 TWX: (910) 498·2203Burlingame 94010: Compar Corp., 820 Airport Blvd.Phone: (415) 347·5411 TWX: (910) 374·236677

PHASE LOCKED LOOP APPLICATIONSCulver City 90230: Hamilton Electro Sales, 10912 W. WashingtonPhone: (213) 559-3311 TELEX: 677-100, 674-381, 674-354EI Monte 91731: G. S. Marshall, 9674 Telstar AvenuePhone: (213) 686-1500 TWX: (910) 587-1565Los Angeles 90022: KT /Wesco Electronics, 5650 Jillson StreetPhone: (213) 685-95'25 TWX: (910) 580-1980Mountain View 94041: Hamilton/Avnet Electronics,340 East Middlefield RoadPhone: (415) 961-7000 TELEX: 348-201Palo Alto 94303: Wesco Electronics, 3973 East Bayshore RoadPhone: (415) 968-3475 TWX: (910) 379-6488San Diego 92111: G. S. Marshall, 7990 Engineer Road, Suite 1Phone: (714) 278-6350 TWX: (910) 587-1565San Diego 92123: Hamilton/Avnet Electronics,5567 Keeny VilJa Rd.Phone: (714) 279-2421San Diego 92123: Kierulff Electronics, 8797 Balboa AvenuePhone: (714) 278-2112 TWX: (910) 335-1182CANADAToronto, Ontario: Cesco Electronics, Ltd., 24 Martin Ross AvenuePhone: (416) 638-5250Montreal, Quebec: Cesco Electronics, Ltd., 4050 Jean Talon WestPhone: (514) 735-5511 TWX: (610) 421-3445Ottawa, Ontario: Cesco Electronics, Ltd., 1300 Carling AvenuePhone: (613) 729-5118Quebec: Cesco Electronics, Ltd., 98 St. Vallier StreetPhone: (418) 524-3518COLORADODenver 80216: Hamilton/Avnet Electronics, 1400 W. 46th AvenuePhone: (303) 433-8551 TELEX: 45872FLORIDAHollywood 33021: Hamilton/Avnet Electronics, 4020 No. 29th Ave.Phone: (305) 925-5401 TELEX: 51-4328Orlando 32805: Hammond Electronics, 911 West Central Blvd.Phone: (305) 241-6601 TWX: (810) 850-4121ILLINOISElmhurst 60126: Semiconductor Specialists, Inc.,195 Spangler Avenue, Elmhurst Industrial ParkPhone: (312) 279-1000 TWX: 254-0169Schiller Park 60176: Hamilton/Avnet Electronics, 3901 Pace CourtPhone: (312) 678-6310 TELEX: 728-330KANSASPrairie Village 66208: Hamilton/Avnet Electronics,3500 West 75th StreetPhone: (913) 362-3250MARYLANDHanover 21076: Hamilton/Avnet Electronics, 7255 Standard Drive,P. O. Box 8647Phone: (301) 796-5000 TELEX: 879-68Rockville 20850: Pioneer Washington Electronics, Inc.,1037 Taft Street Phone: (301) 424-3300MASSACHUSETTSBurlington 01803: Hamilton/ Avnet Electronics207 Cambridge StreetPhone: (617) 272-3060 TELEX: 9494-61Needham Heights 02194: Kierulff/Schley, 14 Charles StreetPhone: (617) 449-3600 TWX: (710) 325-1179MICHIGANLivonia 48150: Hamiiton/Avnet Electronics, 13150 Wayne Rd.Phone: (313) 522-4700Detroit 48240: Semiconductor Specialists, Inc.,25127 W. Six Mile RoadPhone: (313) 255-0300 TWX: (910) 254-0169MINNESOTAMinneapolis 55420: Semiconductor Specialists, Inc.,8030 Cedar Avenue, SouthPhone: (612) 854-8841MISSOURIHazelwood 63042: Hamilton/Avnet Electronics, 400 Brookes LanePhone: (314) 731-1144 TELEX: 442348NORTHERN NEW JERSEYCedar Grove 07009: Hamilton/Avnet Electronics,220 Little Falls RoadPhone: (201) '239-0800 TELEX: 138313SOUTHERN NEW JERSEY AND PENNSYLVANIACherry Hill, N. J. 08034: Hamilton/Avnet Electronics,1608-10 W. Marlton PikePhone: (609) 662-9337 TELEX: 834737Cherry Hill, N. J. 08034: Milgray·Delaware Valley,1165 Marlkress RoadPhone: N.J. (609) 424-1300 Phila. (215) 228-2000TWX: (710) 896-0405NEW YORKBuffalo 14202: Summit Distributors, Inc., 916 Main StreetPhone: (716) 884-3450 TWX: (710) 522-1692Farmingdale, L. I., 11735: Arrow Electronics,900 Broad Hollow Rd.Phone: (516) 995-2100Hauppauge, L.I. 11787: Semiconductor Concepts, Inc.,Engineer RoadPhone: (516) 273-1234 TWX: (510) 227-623'2Syracuse 13211: Hamilton/Avnet Electronics, 222 Boss Rd.Phone: (315) 437-2642Woodbury, L.I. 11797: Harvey Radio, 60 Crossways Park WestPhone: (516) 921-8700 TWX: (510) 221-2184OHIOCleveland 44122: Arrow Electronics, 23945 Mercantile Rd.Phone: (216) 464-2000Cleveland 44105: Pioneer Standard ElectroniCS,5403 Prospect Ave., P. O. Box 05100Phone: (216) 587-3600 TWX: (810) 421·8238Kettering 45429: Arrc N Electronics, 3100 Plainfield RoadPhone: (513) 253-91'6 TWX: (810) 459-1611TEXASDallas 75207: Hamilton/Avnet Electronics, 2403 Farrington Ave.Phone: (214) 638-2850 TELEX: 732359Dallas 75220: Solid State Electronics Company,2643 Manana Dr., P. O. Box 20299Phone: (214) 352-2601Houston 77019: Hamilton/Avnet Electronics,1216 West Clay StreetPhone: (713) 526-4661 TELEX: 762589UTAHSalt Lake City: Alta Electronics, 2280 S. Main St., 84115Phone: (801) 486-7227 TELEX: (910) 925-5282WASHINGTONSeattle 98121: Hamilton/Avnet Electronics, 2320 Sixth AvenuePhone: (206) 624-5930 TELEX: 3224978

PHASE LOCKED LOOP APPLICATIONSINTERNATIONAL SALESEUROPEAN HEADQUARTERSSignetics International Corp., Yeoman House, 63 Croydon Road,Penge, London, S.E. 20, EnglandPhone: (01)6592111 TELEX:946619FRANCESignetics S.A.R.L., 90 Rue Baudin, F 92 Leva"ois-Perret, FrancePhone: 739-85-80/739-96-40 TELEX: 62014WEST GERMANYSignetics GmbH, Ernsthaldenstrasse 17,07 Stuttgart 80, West GermanyPhone: (0711) 73-50-61 TELEX: 7255798STOCKING DISTRIBUTORSAUSTRALIAPye Industries, Ltd., Technico Electronics Division,53 Carrington Rd., Marrickville, Sydney, N.S.W.Phone: 55-0411 TELEX: 790-21490Pye Industries, Ltd., Technico Electronics Divsion,2-18 Normanby Road, South Melbourne, Vic.Phone 69-60-61 TELEX: 31240BELGIUMKlaasing Benelux S.A., 30 Rue Leon Frederic, 1040 BrusselsPhone: (02) 33-62-63, 34-20-30 TELEX: 25003WEST GERMANYEBV Elektronik GmbH. Augustenstrasse 79, 0-8 Muenchen 2Phone: (0811) 52-53-40/48 TELEX: 524535EBV Elektronik GmbH. Myliusstrasse 54 0-6 Frankfurt/Main 1Phone: (0611) 72-04-16/18 TELEX: 413590EBV Elektronik GmbH. Scheurenstrasse I, 0-4 DuesseldorfPhone: (0211) 8-48-46/47 TELEX: 8587267"Muetron" Muller & Co. KG, Postfach 164, Bornstrasse 65,0-28 Bremen 1Phone: (0421) 31-04-85 TELEX: 245-325Omni Ray Gmbh, Moltkestrasse 8, 67 LudwigshafenPhone: (062151) 3055 TELEX:0464557Oistron GmbH, 0-1 Berlin 31, Wilhelmsaue 39-41Phone: 0311/870144 TELEX: 18-27-58Signetics GmbH, Eulenkrugstr, 81 E, 0-2 Hamburg 67Phone: (411) 60-35-242AUSTRIAIng. Ernst Steiner, Beckgasse 30, A-1130 WienPhone: (222) 82-10-605SWITZERLANDDewald AG, Seestrasse 561, CH 8038, ZuerichPhone: (051) 45-13-00 TELEX: 52012Omni Ray AG, Dufourstrasse 56, 8008, ZurichPhon~01~40766 TELEX: 53239FRANCES. A. Gallec Electronique, 78, Avenue des Champs-Elysees,Paris 8e Phone: 359-58-38/255-67-10/255-67-11R.T.F., 73, Av. de Neuilly, 92 - Neuilly sur Seine, ParisPhone: 722.70.40 TELEX: Q5.933Elic 38, Ie Bureau Barisien S.A.R.L,8-10 Avenue du Grand Sablon, 38 La TronchePhone: (76) 87·67·71 TELEX: 32-739ITALYMetroelettronica S.A.S., Viale Cirene 18, 1-20135 MilanoPhone: 546-26-41 TELEX: 33-168 MetronicISRAELRapac Electronics Ltd., P. O. Box 18053, 15 Karl Herbst St.,Tel-Baruch, Tel-Aviv Phone: 77 71 15,6,7 TELEX: TV 528UNITED KINGDOMQuarndon Electronics Ltd., Slack Lane, Derby, DerbyshirePhone: (0332) 3 26 51 TELEX: 37163S.O.S. (Portsmouth) Ltd., Hilsea Industrial EstatePortsmouth, HampshirePhone: 6 53 11 TELEX: 86114Semicomps Ltd., 5 Northfield Industrial Estate,Beresford Ave., Wembley, MiddlesexPhone: (01) 903-3161 TELEX: 935'243A. M. Lock & Co. Ltd., 79 Union St., Oldham, Lancs, EnglandPhone: 061-624-6832SCOTLANDSemicomps Northern Ltd., 44, The Square, Kelso, RoxburghshirePhone:2366 TELEX:72692SWEDEN, NORWAY, FINLANDA. B. Kuno Kallman, Jarntorget 7, S-413 04 Goteberg SV,Phone: 17-01-20 TELEX: 21072DENMARKE. Friis-Mikkelsen A/S, Krogshojvej 51, DK-2880 BagsvaerdPhone: (01) 986333 TELEX:2350THE NETHERLANDSMulder·Hardenberg, P. O. Box 5059, Westerhoutpark I-A, HaarlemPhone: (023) 3191 84 TELEX: 41431JAPANAsahi Glass Co., Ltd., 1-2 Marunouchi, 2 Chome Chiyoda-ku, TokyoPhone:218-5536 TELEX:4616AFRICAAllied Electronic (PTY) Ltd., P. O. Box 6090,Dunswart, Transvaal, South Afri·caPhone: 544341 TELEX: 43-7823REPRESENTATIVESSWEDEN, NORWAY, FINLANDA. B. Kuno Kallman, Jarntorget 7, S-413 04 Goteborg SV, SwedenPhone 17-01-20 TELEX: 21072ISRAELRapac Electronics Ltd., P. O. Box 18053, 15 Karl Herbst St.,Tel-Baruch, Tel-Aviv Phone: 77 71 15,6,7 TELEX: TV 528JAPANAsahi Glass Co., Ltd., 1-2 Marunouchi, 2 Chome,Chiyoda-ku, Tokyo Phone 218-5536 TELEX: 4616SWITZERLAN DDewald AG, Seestrasse 561, CH 8038 ZuerichPhone: (051) 45-13-00 TELEX: 52012INDIASemiconductors Limited, Radia House, 6, Rampart Row,Fort, Bombay - 1Phone: 293667 TELEX: Transducer, Bombay79

0314 LlN·005·62 50M80Printed in U.S.A.