CompuScope SDK Manua.. - Egmont Instruments

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Plug-n-Play is an inherent part of the PCI specifications. Any add-on cards, which do not adhere to itsprotocols, are not PCI-compliant.DMA or Bus-Mastering on the PCI BusDirect Memory Access (DMA) is a technique by which two system resources on a bus can transfer databetween themselves without any CPU involvement.In the PCI bus specification, these two devices are called “initiator” and “target,” i.e. the initiator devicetakes control of the data, address and control lines of the bus and writes the data to the target device.The PCI Bus implements DMA by allowing any device to become a bus-master and write data to a targetdevice. The correct PCI language for DMA is PCI bus-mastering.A PCI Bus-master is a hardware device that takes control of the data, address and control lines of the busand uses them to transfer data to a target device. A PCI Slave is a hardware device in a bus-based systemthat accepts data transfers coming from a Master. A slave is almost always a “target” device.A good analogy of bus-mastering exists in most businesses in the shape of a telephone system. Officesgenerally have a receptionist who answers all incoming calls and directs them to different employees,depending on whom the caller wants to talk to.This is a good example of Slave mode operation. The receptionist is the “Central Processing Unit (CPU)”of the system, all the employees are “target devices” and the caller is the “initiator.”Slave mode does not require very sophisticated hardware, but requires considerable “processing power”(the receptionist’s time) and slows down the routing of the “transactions” (calls).Some companies have implemented “Direct Inbound Dialing (DID)”, a system in which each employee hasa unique telephone number. A caller can reach an employee, without having to go through the receptionist,by dialing their number.DID is analogous to bus-mastering: the “initiator” (caller) takes control of the bus (the telephone line) andconnects with the “target” (employee) without having to disturb the CPU (receptionist).It is fairly clear that bus-mastering is more efficient not only because the CPU (receptionist) can do othertasks while all the bus transactions (calls) take place, but also because it is faster.The obvious question, which arises in the case of a Multi-Master bus, is; how is the bus arbitrated? In otherwords, how does the system know who is the current bus-master and how does a device become a busmaster?The arbiter is always included with the motherboard or CPU card. Unfortunately, there is no clearspecification for bus arbitration in PCI, so the exact schemes are dependent upon the motherboard or CPUbeing used. Nonetheless, bus arbitration is almost always handled in a safe and predictable manner,making PCI a very stable and well-defined system.The PCI bus allows any of the system resources to become a bus-master. For example, it is possible for anadd-on card, such as a CompuScope/PCI, to be a master at one point in time and another add-on card, suchas a DSP card, to be the master at a later time. Naturally, the CPU is also allowed to be the bus-master.Page 12CompuScope SDK Manual
Memory Mode Operation of the PCI Bus CompuScopeCardsIn memory mode, PCI Bus CompuScope cards digitize the analog signal and store the resulting digital datain on-board memory. This memory can be accessed by the CPU (or any other PCI device) only after theacquisition has stopped.A/DRAMP C I B U SOn-board CompuScope memory is therefore single-port memory. If the A/D is writing into it, neither theCPU nor any other PCI device can access it.The on-board memory is designed to accept data from the A/D converters at the highest sampling speeds ofthe card. For example, the on-board memory on CompuScope 8500 has a cycle time of 2 nanoseconds per8 bit sample, or 500 MB/s.The maximum record length of the signal being captured by a PCI bus CompuScope card is determined bythe amount of on-board memory. The captured data can than be transferred to the PC memory at the speedallowed by the PCI bus. In bus-mastering mode, a CompuScope card is capable of sustained PCI datatransfer rates of up to 100 Megabytes/sec (depending on the motherboard). In Slave mode, the transfer rateis up to 10 Megabytes/sec.Data throughput across the PCI BusThe PCI bus is capable of transferring data from an add-on card to the CPU memory using either Slave orMaster moves. PCI Bus CompuScope cards allow both types of data transfers to take place. Anapplication program can select which mode to use by using a driver function. This driver function writesthe appropriate control words into the PCI controller on-board the CompuScope/PCI cards.Number of PCI Slots in one ChassisThe PCI bus can usually have no more than 3 or 4 add-on slots, due to the unterminated nature of the bus.Each add-on device has strict restrictions on how much it can load the bus.It is possible to have more than 3 or 4 PCI slots on the same backplane if the slots are part of differentbuses (called peer buses) and each bus has no more than 3 or 4 peer slots. For instance, a Gage InstrumentMainframe is available with 16 contiguous PCI slots.CompuScope SDK Manual Page 13
Page 1 and 2: Volume I:CompuScope C/C++Software D
Page 3 and 4: Gage Applied Technologies, Inc. Sof
Page 5: Global Table of ContentsVolume I Co
Page 8 and 9: Chapter 5: Sample ProgramsWindows S
Page 11 and 12: PrefaceImportant Notes:• The Comp
Page 13: Chapter 2: BasicCompuScopeOperation
Page 16 and 17: CompuScope A/D cards generally oper
Page 18 and 19: Multiple CompuScope SystemsThe Comp
Page 22 and 23: On-Board MemoryOrganization of theC
Page 24 and 25: memory counter overflow rolls over
Page 26 and 27: If during the data acquisition the
Page 28 and 29: On-board Memory: A Programmer’s V
Page 30 and 31: CompuScope RepetitiveCapture Perfor
Page 32 and 33: depth portion of the single channel
Page 34 and 35: Page 26CompuScope SDK Manual
Page 36 and 37: Sample Programs Folder Structure us
Page 38 and 39: • Gage_drv.hGage_drv.h contains g
Page 41 and 42: Writing a C Application forCompuSco
Page 43 and 44: The last routine, gage_trigger_cont
Page 45: Chapter 5:Sample Programs
Page 48 and 49: Program NameA2D_PAGED_TRANSFER.EXED
Page 50 and 51: Flow Chart describing the sample pr
Page 52 and 53: gage_trigger_control_2:gage_set_ext
Page 54 and 55: GAG2A2D_MUL_BM.EXEThe sample progra
Page 56 and 57: Gage API routines used:gage_get_dri
Page 58 and 59: DIGITAL_INPUT.EXEThe sample program
Page 61: Chapter 6:Appendices
Page 64 and 65: uInt32 sample_rate;void far *memptr
Page 66 and 67: trigger_level level at which trigge
Page 68 and 69: trigger_sensitivitytrigger_bandwidt
Page 70 and 71:
Settings for boarddef structure fie
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10 KHz SRTI_10_KHZ5 KHz SRTI_5_KHZ2
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• couple_eThe parameter couple_e
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Example:Below is illustrated a typi
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Appendix C: CompilingCompuScope SDK
Page 81:
Creating a new LabWindows CVI proje
Page 84 and 85:
Arbitrary Waveform GenerationOne co
Page 86 and 87:
Technical SupportGage Applied Techn
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