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LOGIC SYMBOLS5. EXPLANATION OF A TYPICAL SYMBOL FOR A DYNAMIC MEMORY5.1 THE TMS 4116 SYMBOL....;(5"";) __ -1 20D7/2100AO (7)~! (6)A3 (12)A4 (11)A5 (10)A6 (13)TMS 4116RAM 16K X 1oA16383The TMS 4116 symbol will be explained in detail for eachoperating function. The assumption is made that Sections2 and 4 have been read and understood. While this symbolis complex, so is the device it represents and the symbolshows how the part will perform depending on the sequencein which signals are applied.RAS _(....;4) .... --1CAS_(1_5~)~~------~23C22TN (3)D (2)A,22DA\l(14) Qr-0CCIc:;'til'
lOGIC SYMBOLSWhen RAS goes low, it momentarily enables (through C20, I> indicates a dynamic input) the D inputs of the sevenaddress registers 7 through 13. When CAS goes low, it momentarily enables (through C21) the D inputs of the sevenaddress registers 0 through 6. The outputs of the address registers are the 14 internal address lines that select 1 of16,384 cells.5.3 REFRESHRAS4lREFRESH RowlWhen RAs goes low,row refresh starts. It ends when RAS goes high. Theother input signals required to carry out refreshing are not indicated bythe symbol.5.4 POWER DOWNRAS ~ 24 [PWR DWNlCAS ----1 G24 .CAS is AND'ed with RAs (through G24) so when RAS and CAS are bothhigh, the device is powered down.5.5WRITERASCASiND23C22By virtue of the AND relationship between CAS and iN (explicitly shown),when either one of these inputs goes low with the other one and RAs alreadylow (RAS is AND'ed by G23), the D input is momentarily enabled(through C22). In an "early-write" cycle it is W that goes low first; thiscauses the output to remain off as explained below.5.6READCAS--e.......,&.;~C21G24RAS --....... ~ G23iN ----I 23,21 D '24EN1----..... A\lIf you have questions on this Explanationof New Logic Symbols, please contact:F.A. Mann MS 49Texas Instruments IncorporatedP.O. Box 225012Dallas, Texas 75265Telephone (214) 995-2867QThe AND'ed result of RAS and iN (produced by G23) isclocked into a latch (through C21) at the instant CAS goeslow. This result will be a "1" if RAS is low and iN is high.The complement of CAS is shown to be AND'ed with theoutput of the latch (by G24 and 24). Therefore, as long asCAS stays low, the output is enabled. In the "early-write"cycle referred to above, a "0" was stored in the latch by Wbeing low when CAS went low, so the output remaineddisabled.IEEE Standards may be purchased from:Institute of Electrical and Electronics Engineers, Inc.345 East 47th StreetNew York, N.Y. 10017International Electrotechnical Commission (lEC)publications may be purchased from:American National Standards Institute,lnc.1430 BroadwayNew York, N.Y. 10018tn'0.cE>en(.)'0,o...I184TEXAS INSTRUMENTS 10-5INCORPORATEDPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
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TMS446465,536-WORD 8Y 4-81T DYNAMIC
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TMS446465,536·WORD BY 4·BIT DYNAM
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1MS446465,536·WORD BY 4·B11 DYNAM
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TMS446465,536·WORD BY 4·BIT DYNAM
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RASCAS----{! '.,ReIVIH i~VIL I tRLC
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~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
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~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
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MEMORY SUPPORTLSITMS4500ADYNAMIC RA
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TMS4500ADYNAMIC RAM CONTROLLERpin d
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TMS4500ADYNAMIC RAM CONTROLLERarbit
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TMS4500ADYNAMIC RAM CONTROLLERswitc
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TMS4500ADYNAMIC RAM CONTROLLERacces
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TMS4500ADYNAMIC RAM CONTROLLERoutpu
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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•••••MOSLSI65,536 X 4 Org
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TM4164EC465,536 BY 4·BIT DYNAMIC R
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MOSLSITM4164EL965,536 BY 9·BIT DYN
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TM4164EL965,536 BY 9-BIT DYNAMIC RA
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••••••••0MOSLSI65,5
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TM4164FL865,536 BY 8·BIT DYNAMIC R
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MOSLSITMS2516. SMJ251616.384-BIT ER
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TMS2516, SMJ251616,384-BIT ERASABLE
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TMS251616,384·BIT ERASABLE PROGRAM
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SMJ251616,384-BIT ERASABLE PROGRAMM
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o 441MS2516, SMJ251616,384·B11 ERA
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MOSLSITMS2532, SMJ253232,768·BIT E
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TMS253232,768-BI1 ERASABLE PROGRAMM
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MOSLSITMS2564, SMJ256465,536-BIT ER
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TMS256465,536-BIT ERASABLE PROGRAMM
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TMS2564 r SMJ256465 r536-BIT ERASAB
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MOSLSITMS2708, TMS27L08, SMJ2708, S
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TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
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TMS2708. TMS27L081024·WORD BY 8·B
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SMJ2708, SMJ27L081024·WORD BY 8·B
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TMS2708, TMS27L08SMJ2708, SMJ27L081
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MOSLSITMS27162048·WORD BY 8·BIT E
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TMS27162048·WORD BY 8·BIT ERASABL
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TMS27162048-WORD BY 8-BIT ERASABLEP
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TMS2732A32,76B-BIT ERASABLE PROGRAM
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TMS2732A32,768-BIT ERASABLE PROGRAM
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TMS2732A32,768·BIT ERASABLE PROGRA
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MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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MOSLSITMS46648192·WORD BY 8·BIT R
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TMS46648192·WORD BY 8·BIT READ·O
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MOSLSITMS47324096~WORD BY B·BIT RE
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MOSLSITMS47648192·WORD BY 8·BIT R
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MOSLSI, TMS49648192·WORD BY 8·BIT
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MOSLSITMS4712816,384·WORD BY 8·BI
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TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384-WORD BY 8-BIT READ-O
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MOSLSITMS4725632.768·WORD BY 8·BI
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TMS4725632.768·WORD BY 8·BIT READ
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MOSLSITMS2114, TMS2114L1024·WORD B
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TMS2114, TMS2114L1024·WDRD BY 4·B
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TMS2114. TMS2114L1024·WORD BV 4·B
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ADVANCED MEMORYDEVELOPMENT•Fast A
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TMS2150CACHE ADDRESS COMPARATORabso
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TMS2150CACHE ADDRESS COMPARATORPARA
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MOSLSITMS40162048·WORD BY 8·BIT S
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TMS4016204H-WORD BY H-BIT STATIC RA
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TMS40162048-WDRD BY 8-BIT STATIC RA
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MOSLSITMS4044, TMS40L444096-WORD BY
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TMS4044, TMS40L444096·WORD BY 1·B
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TMS4044, TMS40L444096·WORD BY l·B
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MILITARYCMOSLSISMJ55172048-WORD BY
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SMJ5517204a·WORD BY a·BIT STATIC
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SMJ55172048·WORD BY 8·BIT STATIC
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SMJ55172048-WDRD BY 8-BIT STATIC RA
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SMJ5517204B·WORD BY B·BIT STATIC
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However, the TMS 4164 provides the
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EXPANSION OF 3242 FOR 256-CYCLE REF
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•9-6
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PAD OPENINGIN OVERCOATPADMETALPADME
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Figure 5 shows how the driver outpu
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cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
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The falling edge of RAS causes R 1
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~--------::~~:~:~~~:--------~~7,34(
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J-Lead AdvantageTexas Instruments P
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Surface Mount Component Availabilit
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fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
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l>'C'2.ri'Q),..o·:::Jen5'....... o
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l>"C'2..(i"Dl...0":=(I)5"....o...3D
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An external refresh counter has bee
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l>'C'CC:)"Q).-+o·::::sen:ro ... ""
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uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
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B. If dynamic RAM refresh is enable
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•9-38
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The TMS4416/TMS4500A board is arran
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RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
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9-44
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ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
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The ALE high to ClK low time is giv
Page 400 and 401: ClKALEACXRASMAO-MA7CASREFREQROY•
Page 402 and 403: CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
Page 404 and 405: UO!leWJOJUI SUOlle:ludd"com~'~,i'74
Page 406 and 407: coen(J)CLOCKWRITEREADROYALEA14-A5MS
Page 408 and 409: . Access Grant CyclesThe precharge
Page 410 and 411: whereta(C)tp(BFR)(-103 + tc2 - tp(B
Page 412 and 413: •9-62
Page 414 and 415: tt(REH)TCHLLtAEL-RELRAS rise time (
Page 416 and 417: . Refresh CyclesOn refresh cycles t
Page 418 and 419: wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
Page 420 and 421: R/W approach does a normal read-mod
Page 422 and 423: II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
Page 424 and 425: ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
Page 426 and 427: 4. Row address setup and hold timeT
Page 428 and 429: CLKrWRITE -------I.~ ..~---REFRESH-
Page 430 and 431: The read access time on access gran
Page 432 and 433: implementations in order to relieve
Page 434 and 435: "C'2..c:rm...o·j(I)....5'o3...mo·
Page 436 and 437: RELATIVE MEMORY SIZEARCHIVAL STORAG
Page 438 and 439: increments till satisfied. This pro
Page 440 and 441: In the example shown in Figure 5, t
Page 442 and 443: »'C"E..crQ)r+0':::Jtil:;-....o...3
Page 444 and 445: •9-94
Page 447 and 448: 184LOGIC SYMBOLS1. INTRODUCTIONEXPl
Page 449: LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
Page 453 and 454: Alphanumeric Index, Table of Conten
Page 455 and 456: MECHANICAL DATAgeneralElectrical ch
Page 457 and 458: MECHANICAL DATAceramic packages -ce
Page 459 and 460: MECHANICAL DATAplastic packages (N
Page 461 and 462: MECHANICAL DATAceramic chip carrier
Page 463 and 464: Texas InstrumentsSemiconductor Tech
Page 465 and 466: TI Sales Offices TI DistributorsALA
Page 468: Printed in U.S.A.•TEXASINSTRUMENT
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