1 - Al Kossow's Bitsavers

184LOGIC SYMBOLS1. INTRODUCTIONEXPl.ANATION OF NEW LOGIC SYMBOLSFOR MEMORIESThe International Electrotechnical Commission (lEC) has been developing a very powerful symbolic language that canshow the relationship of each input of a digital logic circuit to each output without showing explicitly the internallogic. At the heart of the system is dependency notation, which will be partially explained below.The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard Y32.14-1973. Lacking at thattime a complete development of dependency notation, it offered little more than a substitution of rectangular shapesfor the familiar distinctive shapes for representing the basic functions of AND, OR, negation, etc. This is no longerthe case.Internationally, IEC Technical Committee TC-3 has prepared a new document (Publication 617-12) that will consolidatethe original work started in the mid 1960's and published in 1972 (Publication 117-15) and the amendments and supplflmentsthat have followed. Similarly for the USA, I EEE Committee SCC 11.9 has revised the publication IEEEStd 91/ANSI Y32.14. Texas Instruments participated in the work of both organizations and this 1984 Edition of theMOS Memory Data Book introduces new logic symbols in anticipation of the new st~ndards. When changes are made asthe standards develop, future editions of this book will take those changes into account.The following explanation of the new symbolic language is necessarily brief and greatly condensed from what thestandards publiGCItions will finally contain. This is not intended to be sufficient for those people who will be developingsymbols for new devices. It is primarily intended to make possible the understanding of the symbols used in this book.2. EXPLANATION OF A TYPICAL SYMBOL FOR A STATIC MEMORYThe TMS 2114 symbol will be explained in detail. This symbol includes almost all the features found in the others.Section 4, oiagramatic Summary, should be referred to while reading this explanation.TMS2114RAM102Ax4By convention all input lines are located on the left and output lines arelocated on the right. When an exception is made, an arrowhead shows reversesignal flow. The input/output lines (001 through 004) illustrate this.The polarity indicator ~ indicates that the external low level causes theinternal 1 state (the active state) at an input or that the internal 1 state causesthe exte[nal low level at an output. The effect is similar to specifying positivelogic and using the negation symbol 0 •The rest of this discussion concerns features inside the symbol outline. Theaddress inputs are arranged in the order of their assigned binary weights andthe range of the addresses are shown as A r:; where m is the decimal equivalentof the lowest address and n is the highest. The inputs and outputs affected bythese addresses are designated by the letter A.en'0.QE>­en'e»The letter Z followed by a number is used to transfer a signal from one point (,)in a symbol to another. Here the signal at output A,Z3 transfers to the 3 atthe left side of the symbol in order to form an inpot/output port. The A .9means the output comes from the storage location selected by the addressinputs. _.The 'V symbol designates a three·state Ol,ltput. Three-state outputs will always .be controlled by an EN function. When EN stands at its internal 1 state, theoutputs are enabled. When EN stands at its internal 0 state, the three-stateoutputs stand at their high·impedance states.TEXAS INSTRUMENTS 10-1INCORPORATEDPOST OFFICE BOX 225012 • OALLAS, TEXAS 75265