1 - Al Kossow's Bitsavers

In the example shown in Figure 5, the expansion of the cache RAM is carried out in both depth (more sets) and width (widertag). The block size has been chosen as one such that the 1 K cache now represents 1024 blocks of one word each. Thehigh order addresses are still used as the label to the tag RAM but now A9 is used to select between two TMS2150 pairseach containing labels for 512 of the cache memory blocks. Addresses lines AO - A8 are thus used as the set addressinputs. If the chip select (S) is at logic one (deselected), the TMS2150 match output (M) is high, so an AND gate can beused to enable the cache data buffers and also to notify the control circuit if access needs to be made into the main memory.The logic for this system is shown so that the upper pair is compared for the first 512 blocks within cache and the lowerpair is compared for the second depending on the state of address A9.ADDRESSES TOCACHE BUFFER RAMMATCH OUTPUT TOBUFFER ENABLEPROCESSORA9 AO-AB Al0-A16MAINMEMORYUP TO32M BYTES............ +------+--------iM STMS2150.-~~---------+---------------~sl>"'C"En·0)...o·::Jen:;-....o30)...o·::JFIGURE 5 -BLOCK SIZE = 1CACHE MEMORY CONFIGURATION9-90