1 - Al Kossow's Bitsavers

Since the label in this example is composed of 1 5 address lines, two TMS21 50s are used as an expanded tag. The 1 5 addresslines are the data inputs to the tag RAM and the 16th data input is tied to + 5 V so that after RESET invalid data cannotforce a match. The match output of the two TMS2150s are ANDed together to form the enable for the cache data buffer. Inthis manner, if the contents of either TMS21 50 does not contain a match, the cache is not enabled. This ANDed MATCHsignal is also used by the control circuitry to notify the system that the address is not present in the cache so that mainmemory might be accessed. The control circuit is also responsible for the reseting of the cache upon power-up, which is accomplishedwith a low pulse on the RESET input of the TMS21 50. After reset, no matches will occur at any locations untilthat location has been written ..A00-07PROCESSOR4OQ1-DQ4 •1K)(4RAMBUFFER•E..., .4OQ1-0Q41K)(4RAMMAINMEMORYUPTO32M BYTESAO-A910~'1AO-A9AO-A24AO-A9'lOt1 AO-A99{1-A9 7 +S V 9't' -A9 B~ A17-A24,A10-A1eCDO - De 07 "'--""':0:"!0~-1.:0~7~--"AO - AB AO - AB --;:::0-~~i _____ T_M_·~T2~1_60_____ M.. ~ ~~i _____ T_M_:'~2~1_601CONTROL(RESET. W. PElBLOCK SIZE = Z_____FIGURE 4 - CACHE MEMORY CONFIGURATIONM~ I _......co'';::CO.. Eo~.Eenco'';::CO,~Q.c.