1 - Al Kossow's Bitsavers

increments till satisfied. This processor using 150 ns DRAMs would require one delay increment on main memory accessesand 200 ns DRAMS would require two delay increments. The average cycle time can be calculated for each memory speedas follows:Average .CY'cle Time = [(INT) x (CYC)] + [(MEM) x (CYC + DEL))where INT = percent of time doing internal operationsCYC = processor cycle timeMEM = percent of time doing memory accessesDEL = number of delay increments x 100 nsFor a processor using 150 ns DRAMs:Average Cycle Time = [(70%) x (250 ns)) + [(30%) x (250 + 100))= 280 nsFor a processor using 200 ns DRAMs:Average Cycle Time = [(70%) x(250 ns))+[(30%) x(250+200))= 310 nsFor the same system with cache memory assume a 90% hit ratio with 75 ns cache and 200 ns DRAM:Average Cycle Time = [INT x CYC) + [MEM x [(HIT x CAC) + (MIS x (CYC + DEL))))where INT = percent of time doing internal operationsCYC processor cycle timeMEM = percent of time doing memory accessesDEL = number of delay increments x 100 nsHIT = percent of memory accesses hit cacheMIS = percent of memory accesses miss cacheCAC = cache memory access cycle timeAverage Cycle Time = [70% x 250) +[30% x [(90% x 250) + (1 0% x (250 +200))))= 253 nsThis value represents a 10% improvement with 200 ns devices over the non-cache implementation with 150 ns parts and18% using 200 ns parts. This performance improvement can be further demonstrated for those systems using custom orbit-slice processors where the memory cycle time as well as access time is of concern. For this example, consider a processorwith a cycle time of 50 ns and main memory cycle time of 250 ns (use the same access ratios as in the previousexample):ACT (Without Cache) = [(70%) x (50)) + [(30%) x (250)L= 110 nsACT (With Cache) [70% x 50) + [30% x [(90% x 50) + (1 0% x 250))= 56 nsThis represents a 49% decrease in average cycle time for the processor using 50 ns cache memory. If the main memory wasrated at a cycle time of 500 ns, either using very slow main memory, error detection/correction, or due to allocation of alternatecycles for some other activity (multi-processors, direct memory access, display refresh, etc.); the cache would still givean average cycle time of 63.5 ns, which is an improvement of 65% over the 185 ns average cycle time for a non-cachesystem.The following figures show several applications for TMS2150 in cache memory systems. Figure 4 shows a cache memoryconfiguration that has a 32-megaword main memory (represented as 32-megabytes since only an eight-bit data bus is used)with a block size of 2. In this particular example, a cache containing 512-two word blocks was chosen thus defining themain (n)x(m) array as being 512 sets of 32,768-two word blocks. The 32-megaword memory requires an address bus of25 lines. The least significant address (AO) is used as a word select for one of the two words in each block. The next leastsignifiCant address lines (A 1 - A9) are used as the set select inputs to the cache buffer RAM and the cache tag RAM.The remaining high order address lines (A 10 - A24) form the label or tag which is stored and compared by the tag RAM.9-88