1 - Al Kossow's Bitsavers

implementations in order to relieve the processor of wait states when accessing memory. ApplicationsNotes SR-1 , "An Introduction To Cache Memory Systems And The TMS2150", and DRC-1,"The TMS4500A In An Asynchronous Bus System", address the concepts of cache and asynchronousmemory architecture in more detail than given here.The percentage of time a microprocessor uses for internal operations as opposed to memory accessesis also a factor in determining system throughput when wait states_ are used. The greater the percentageof time that a microprocessor spends accessing memory with wait states, the greater thethroughput degradation. Thus, for systems whose software requires extensive internal processor operationsand few memory operations it may be more desirable to operate with wait states as opposedto the "Hybrid" approach. Tabl.e 5 gives an example of a few MC68000 instructions and their effecton throughput. The actual average instruction time will be dependent upon the instruction streambeing executed, but this example will indicate how wait states affect the processor performance. Themultiply and divide instructions which require a large percentage of internal operations make apparentthe advantage of higher speed processors when doing extensive numeric processing; however if thememory intensive instructions predominate, the system running without wait states will execute fastereven at slower clock frequencies. Systems which execute program mainly out of EPROM, PROM,ROM and Static memory and only use. DRAM for data storage may also benefit from the use of thehigh speed processors. Each of the four designs has its own niche which is based on the necessarysystem application. Designs that require maximum memory performance and minimum componentcount may find the Hybrid interface more suitable, while systems requiring maximum processor performancewould utilize the MC68000L8/L 10 design.TABLE 5 -AVERAGE INSTRUCTION CYCLE TIMEA. CLOCK CYCLES AND MEMORY CYCLES PER INSTRUCTIONINSTRUCTIONCLOCK CYCLESMEMORY CYCLESPER INSTRUCTION TOTAL PER INSTRUCTION TOTALMOV AN@+ 8 2MOV AN@- 10 2ADD AN@+ 12 2ADD AN@- 14 2CMPI AN@+ 12 3CMPI AN@- 14 3BRA 10 2JMPAN@ 8 2JMP AN@(d) 10 98 2 20MULS 70 168 1 21B. AVERAGE CLOCK CYCLES/INSTRUCTION AND AVERAGE MEMORY CYCLES/INSTRUCTIONNUMBER OF INSTRUCTIONSAVERAGE CLOCK CYCLES/ AVERAGE MEMORY CYCLES/INSTRUCTIONINSTRUCTIONFirst nine instructions 10.8 2.2(excluding MULS)Ten instructions 16.8 2.19-82