1 - Al Kossow's Bitsavers

TABLE 3 -MICROPROCESSOR TO MEMORY CYCLE TIME*MICROPROCESSORCLOCKNUMBER OF WAITCYCLE TIME he)FREQUENCY PERIOD STATES INSERTED (N)MC68000L6 6 MHz 166 ns 664 ns 0MC68000L8 8 MHz 125 ns 625 ns 1MC68000L8 (Hybrid) 7.46 MHz 134 ns 536 ns 0MC68000L 10 10 MHz 100 ns 500 ns 1'tc = 4 (T) + NIT)where T = microprocessor clock periodN = number of wait states inserted.To determine the maximum speed that the MC68000l8 can operate without wait states it is necessaryto recalculate the design criteria using the MC68000l6 equations with MC68000l8 timing parameters(results in Table 4). From these values the restricting parameter will be the ALE to ClK low timing(minimum 10 ns) requirement necessary for proper TMS4500A operation. Setting tCl-AEL equal to12 ns (12 ns allows for 20% margin) and solving for T, yields a clock period of 134 ns (7.46 MHz)The design criteria for 7.46 MHz operation is also shown in Table 4. This "Hybrid" circuit meetsTMS4416-15,-20 and TMS4164-12,-15 timing requirements and has a processor/memory cycle timeapproaching that of the MC68000l1 0 design. This illustration shows the advantage of operatingwithout wait states when accessing DRAM, but does not directly reflect system throughputenhancement.System throughput calculations require a much more detailed analysis taking into consideration thesystems application, use of other types of memory (EPROM, PROM, ROM, and Statics), memory sizeand configuration, software, etc. It is beyond the scope of this application note to cover all of thesevariables in detail, although a brief overview can be given.TABLE 4 -MC68000L8 (HYBRID) DESIGN CRITERIA SUMMARY*DESIGN CRITERIAMICROPROCESSORMC68000L8 @ 6 MHz MC68000L8 @ 7.46 MHz1. Refresh interval 1.95 ms 2.09 ms2. Memory precharge timea. Access cycles (tRP) 167 ns 146 nsb. Refresh cycles (tRP) 189 ns 141 nsc. Access grant cycles (tRP) 170 ns 138 ns3. ALE to CLK relationship 28 ns 12 ns4. Row address setup and hold timesa. To the TMS4500A (tAV-AELl Guaranteed by tAVSL Guaranteed by tA VSLb. To the DRAM (tASR) 17 ns 17 ns5. Data valid to write enable (tDS) 38 ns 38 ns6. Read access time from CASa. Access cycles (tCAC) 180 ns 100 nsb. Access grant cycles (tCAC) 245 ns 165 nss::o'';:;co... E....os::tns::o'';:;co,2Q.c.«'Results reflect gated R/iN operation.All of the interface examples given in this application note used a tightly coupled processor/memoryinterface to maximize DRAM performance. The calculations and comparisons for the "Hybrid" circuitonly reflect that the processor is executing strictly out of DRAM which is not always the casein many sys,tems. As microprocessor speeds and memory size increase, the benefits Of the tightlycoupled memory array give way to asynchronous main memory configurations and cache memory9-81