1 - Al Kossow's Bitsavers

The read access time on access grant cycles for the gated R/W configuration is given by:tCAC 2.5(T) - tCH-CEL - tt(CEL) - tDICLtCAC 2.5(100) - 140 - 15 - 15) ns= 80 nsMC68000L8 Design Calculations ResultsThe results for'the calculations of the design criteria for the MC68000LS are given in Table 1.TABLE 1 -MC68000LS DESIGN CRITERIA SUMMARYDESIGN CRITERIAMC68000L81. Refresh interval 1.95 ms2. Memory precharge timea. Access cycles (tRP) 203 nsb. Refresh cycles (tRP) 122 nsc. Access grant cycles (tRP) 129 ns3. ALE to ClK relationship Guaranteed by clocking AS Iowan the rising edge ot'cp4. Row address setup and hold timesa. To the TMS4500A (tAV-AEl) 93 nsb. To the DRAMs (tASR) 79 ns5. Data valid to write enable (tDS) 38 ns6. Read access time from CASa. Access cycles (tCAC) 149 nsb. Access grant cycles (tCAC) 142 nsThe proper choice of memory can be selected from Table 2 for each design. For the MC68000L6and MC68000L8 designs there are no memory speed restrictions. However, the MC68000L 10 designis restricted to only TMS4416-15 and TMS4164-12 devices; the limiting parameters being RASprecharge (tRP) and CAS access time (tCAC). To meet slower memory requirements the MC6800L 10clock frequency would have to be reduced. The maximum clock frequency for a desired memory speedcan be determined by substituting in the necessary DRAM timing parameters and solving for the inputclock period (T) in the design criteria for memory precharge time and read access time.TABLE 2 -MEMORY SELECTIONMICROPROCESSORMEMORY DEVICESCLOCKTMS4416 TMS4164FREQUENCY-15 -20 -12 -15 -20MC68000l6 6 MHz ~ ~ ~ ~ ~MC68000l8 8 MHz ~ ~ ~ ~ ~MC68000l8 (Hybrid) 7.46 MHz ~ ~ ~ ~MC68000l10 10 MHz ~ ~Meeting DRAM timing requirements is only a small part of microprocessor system design. The ultimategoal is to achieve maximum performance with minimum hardware. Of the three designs the MC68000L6interface requires the least amount of hardware while the MC68000L 10 interface has the fastest processor/memorycycle time. To capitalize on the best of both designs a compromise can be made bysubstituting a MC68000L8 into the MC68000L6 design and operating at less than' 8MHz withoutwait states. Operating under these conditions it can be shown that the processor/memory cycle timeapproaches that of the MC68000L 10 design with a minimum hardware interface (see Table 3).9-80